📄 alt_cusp72_pc.vhd
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IF (reset = '1') THEN
d2_pc_int_1 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d2_pc_int_1 <= d2_pc_int_0;
END IF;
END IF;
END PROCESS;
pc_int <= d2_pc_int_1;
pcf <= pc_to_store;
d2_explicit: IF (INFER_MEMORY = 0) GENERATE
altsyncram_component : altsyncram
GENERIC MAP (
operation_mode => "ROM",
width_a => PCW_WIDTH,
widthad_a => PC_WIDTH,
numwords_a => PC_NUM_WORDS,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
address_aclr_a => "CLEAR0",
read_during_write_mode_mixed_ports => "DONT_CARE",
ram_block_type => "AUTO",
init_file => PROGRAM_FILE,
intended_device_family => "Stratix"
)
PORT MAP (
clocken0 => ena_pc,
aclr0 => reset,
clock0 => clock,
address_a => pc_to_store,
q_a => pcw_from_store
);
pcw <= pcw_from_store;
END GENERATE; -- not INFER
end GENERATE; -- ALTERA LATENCY=3
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
-- d2a: if ( LATENCY = 31) GENERATE -- This is the 3a case
--
-- jump_plus_one : PROCESS(nextpc)
-- BEGIN
-- d2a_jump_plus_one_out <= std_logic_vector(UNSIGNED(nextpc) + 1);
-- END PROCESS;
--
-- jump_plus_one_reg : PROCESS(clock, reset)
-- BEGIN
-- IF(reset = '1') THEN
-- d2a_jump_plus_one_reg_out <= (OTHERS=>'0');
-- ELSIF (clock'EVENT AND clock = '1') THEN
-- IF (ena_pc = '1') THEN
-- IF (load_pc = '1') THEN -- can get rid of this conditional if that improves fmax
-- d2a_jump_plus_one_reg_out <= d2a_jump_plus_one_out;
-- ELSE
-- d2a_jump_plus_one_reg_out <= d2a_jump_plus_one_reg_out;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- pc_inc_mux : PROCESS(d2a_load_pc_d1)
-- BEGIN
-- IF(d2a_load_pc_d1 = '1') THEN
-- d2a_inc <= std_logic_vector(TO_UNSIGNED(2, PC_WIDTH));
-- ELSE
-- d2a_inc <= std_logic_vector(TO_UNSIGNED(1, PC_WIDTH));
-- END IF;
-- END PROCESS;
--
-- pc_add : PROCESS (d2a_pc_reg_out, d2a_inc)
-- BEGIN
-- d2a_pc_add_out <= std_logic_vector(UNSIGNED(d2a_pc_reg_out) + UNSIGNED(d2a_inc));
-- END PROCESS;
--
-- pc_reg : PROCESS (clock, reset)
-- BEGIN
-- IF(reset = '1') THEN
-- d2a_pc_reg_out <= (OTHERS=>'0');
-- ELSIF (clock'EVENT AND clock = '1') THEN
-- IF (ena_pc = '1') THEN
-- IF (load_pc = '1') THEN
-- d2a_pc_reg_out <= nextpc;
-- ELSE
-- d2a_pc_reg_out <= d2a_pc_add_out;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- load_pc_d1_reg : PROCESS (clock, reset)
-- BEGIN
-- IF(reset = '1') THEN
-- d2a_load_pc_d1 <= '0';
-- ELSIF (clock'EVENT AND clock = '1') THEN
-- IF (ena_pc = '1') THEN
-- d2a_load_pc_d1 <= load_pc;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- mux0 : PROCESS (d2a_load_pc_d1, d2a_pc_reg_out, d2a_jump_plus_one_reg_out)
-- BEGIN
-- IF(d2a_load_pc_d1 = '1') THEN
-- d2a_mux0_out <= d2a_jump_plus_one_reg_out;
-- ELSE
-- d2a_mux0_out <= d2a_pc_reg_out;
-- END IF;
-- END PROCESS;
--
-- mux1 : PROCESS (load_pc, nextpc, d2a_mux0_out)
-- BEGIN
-- IF(load_pc = '1') THEN
-- d2a_mux1_out <= nextpc;
-- ELSE
-- d2a_mux1_out <= d2a_mux0_out;
-- END IF;
-- END PROCESS;
--
-- pc_to_store <= d2a_mux1_out;
--
-- pc_shadow_reg_0: PROCESS (clock, reset) -- shadow of RAM input register
-- BEGIN
-- IF (reset = '1') THEN
-- d2a_pc_int_0 <= (OTHERS=> '0');
-- ELSIF clock'EVENT AND clock = '1' THEN
-- IF (ena_pc = '1') THEN
-- d2a_pc_int_0 <= pc_to_store;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- pc_shadow_reg_1: PROCESS (clock, reset) -- shadow or RAM output register
-- BEGIN
-- IF (reset = '1') THEN
-- d2a_pc_int_1 <= (OTHERS=> '0');
-- ELSIF clock'EVENT AND clock = '1' THEN
-- IF (ena_pc = '1') THEN
-- d2a_pc_int_1 <= d2a_pc_int_0;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- pc_shadow_reg_2: PROCESS (clock, reset) -- shadow of second RAM output register
-- BEGIN
-- IF (reset = '1') THEN
-- d2a_pc_int_2 <= (OTHERS=> '0');
-- ELSIF clock'EVENT AND clock = '1' THEN
-- IF (ena_pc = '1') THEN
-- d2a_pc_int_2 <= d2a_pc_int_1;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- pc_int <= d2a_pc_int_2;
--
-- altsyncram_component : altsyncram
-- GENERIC MAP (
-- operation_mode => "ROM",
-- width_a => PCW_WIDTH,
-- widthad_a => PC_WIDTH,
-- numwords_a => PC_NUM_WORDS,
-- lpm_type => "altsyncram",
-- width_byteena_a => 1,
-- outdata_reg_a => "CLOCK0",
-- outdata_aclr_a => "CLEAR0",
-- address_aclr_a => "CLEAR0",
-- read_during_write_mode_mixed_ports => "DONT_CARE",
-- ram_block_type => "AUTO",
-- init_file => PROGRAM_FILE,
-- intended_device_family => "Stratix"
-- )
-- PORT MAP (
-- clocken0 => ena_pc,
-- aclr0 => reset,
-- clock0 => clock,
-- address_a => pc_to_store,
-- q_a => pcw_from_store_int
-- );
--
-- pcw_reg: PROCESS (clock, reset) -- second RAM output register
-- BEGIN
-- IF (reset = '1') THEN
-- pcw_from_store <= (OTHERS=> '0');
-- ELSIF clock'EVENT AND clock = '1' THEN
-- IF (ena_pc = '1') THEN
-- pcw_from_store <= pcw_from_store_int;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- pcw <= pcw_from_store;
-- end GENERATE; -- ALTERA LATENCY=3(derivative)
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
d3: if ( LATENCY = 4) GENERATE
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_width => PC_WIDTH,
lpm_type => "LPM_COUNTER",
lpm_direction => "UP",
lpm_avalue => "0"
)
PORT MAP (
sload => load_pc,
clk_en => ena_pc,
clock => clock,
data => nextpc,
aset => reset,
q => pc_to_store
);
d3check: IF ( DECODE_LATENCY /= 3 ) GENERATE
d3fail: ASSERT false REPORT "For LATENCY=4 DECODE_LATENCY is 3" SEVERITY Failure;
END GENERATE; -- error check
pc_shadow_reg_0: PROCESS (clock, reset) -- shadow of RAM input register
BEGIN
IF (reset = '1') THEN
d3_pc_int_0 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d3_pc_int_0 <= pc_to_store;
END IF;
END IF;
END PROCESS;
pc_shadow_reg_1: PROCESS (clock, reset) -- shadow of RAM output register
BEGIN
IF (reset = '1') THEN
d3_pc_int_1 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d3_pc_int_1 <= d3_pc_int_0;
END IF;
END IF;
END PROCESS;
pc_shadow_reg_2: PROCESS (clock, reset) -- shadow of second RAM output register
BEGIN
IF (reset = '1') THEN
d3_pc_int_2 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d3_pc_int_2 <= d3_pc_int_1;
END IF;
END IF;
END PROCESS;
pc_int <= d3_pc_int_2;
pcf <= pc_to_store;
d3_explicit: IF (INFER_MEMORY = 0) GENERATE
altsyncram_component : altsyncram
GENERIC MAP (
operation_mode => "ROM",
width_a => PCW_WIDTH,
widthad_a => PC_WIDTH,
numwords_a => PC_NUM_WORDS,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
address_aclr_a => "CLEAR0",
read_during_write_mode_mixed_ports => "DONT_CARE",
ram_block_type => "AUTO",
init_file => PROGRAM_FILE,
intended_device_family => "Stratix"
)
PORT MAP (
clocken0 => ena_pc,
aclr0 => reset,
clock0 => clock,
address_a => pc_to_store,
q_a => pcw_from_store_int
);
pcw_reg: PROCESS (clock, reset) -- second RAM output register
BEGIN
IF (reset = '1') THEN
pcw_from_store <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
pcw_from_store <= pcw_from_store_int;
END IF;
END IF;
END PROCESS;
pcw <= pcw_from_store;
END GENERATE; -- not INFER
end GENERATE; -- ALTERA LATENCY=4
dx: IF ( LATENCY > 4 AND LATENCY /= 31 ) GENERATE
unsupported_mode: ASSERT false REPORT "Delay slot parameter not suppported by PC" SEVERITY Failure;
END GENERATE; -- error check
-- Tie off unused outputs
all_infer: IF (INFER_MEMORY /= 0) GENERATE
pcw <= (others => '0');
END GENERATE; -- INFER
END ARCHITECTURE;
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