📄 alt_cusp72_pc.vhd
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TTA_X_D_registerTrace( "??",
"???????",
"????????");
else
TTA_X_D_registerTrace( opAddress(instruction).all,
opCodeVector(instruction).all,
opVector(instruction).all );
end if;
end if;
END;
BEGIN
IF (reset = '1') THEN
loadData;
ELSIF clock'EVENT AND clock = '0' THEN
IF (ena_pc = '1') THEN
reportState;
END IF;
END IF;
END PROCESS;
delayed_pc: PROCESS(clock, reset)
BEGIN
IF (reset = '1') THEN
pc_int_d1 <= (OTHERS=>'0');
ELSIF clock'EVENT AND clock = '0' THEN
IF (ena_pc = '1') THEN
pc_int_d1 <= pc_int;
END IF;
END IF;
END PROCESS;
-- synopsys synthesis_on
-- --------------------------------------------------------------------------------------------
pc_echo: pc <= pc_int;
load_pc_gen: load_pc <= usenextpc AND usenextpc_en AND ena;
--ena_pc_gen: ena_pc <= ena AND NOT ( hold and hold_en);
ena_pc_gen: ena_pc <= (ena OR stall_int) AND NOT ( hold and hold_en);
step_gen: step <= ena_pc;
-----------------------------------------------------------------------------------------------
-- Generate stall during reset and hold stall until first instruction is ready
-----------------------------------------------------------------------------------------------
stall_latency0_gen: IF (LATENCY = 1 or LATENCY = 2) GENERATE
stall_d0 <= reset;
END GENERATE;
stallnext <= stallnext_int;
stall_latency1_gen: IF (LATENCY = 1) GENERATE
stall_int <= stall_d0;
stallnext_int <= stall_d0;
END GENERATE;
stall_latency2_gen: IF (LATENCY = 2) GENERATE
stall_int <= stall_d1;
stallnext_int <= stall_d0;
stall_d1_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d1 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d1 <= '0';
END IF;
END PROCESS;
END GENERATE;
stall_latency3_gen: IF (LATENCY = 3) GENERATE
stallnext_int <= stall_d1;
stall_int <= stall_d2;
stall_d1_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d1 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d1 <= '0';
END IF;
END PROCESS;
stall_d2_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d2 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d2 <= stall_d1;
END IF;
END PROCESS;
END GENERATE;
stall_latency4_gen: IF (LATENCY = 4) GENERATE
stallnext_int <= stall_d2;
stall_int <= stall_d3;
stall_d1_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d1 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d1 <= '0';
END IF;
END PROCESS;
stall_d2_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d2 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d2 <= stall_d1;
END IF;
END PROCESS;
stall_d3_reg : PROCESS(reset, clock)
BEGIN
IF(reset = '1') THEN
stall_d3 <= '1';
ELSIF clock'EVENT AND clock = '1' THEN
stall_d3 <= stall_d2;
END IF;
END PROCESS;
END GENERATE;
d0: IF ( LATENCY = 1) GENERATE
generate_next_pc_int : PROCESS (d0_pc_int_0, nextpc, load_pc)
BEGIN
IF ( load_pc = '1' ) THEN
d0_next_pc_int <= nextpc;
ELSE
d0_next_pc_int <= std_logic_vector(UNSIGNED( d0_pc_int_0) + 1);
END IF;
END PROCESS;
pc_to_store <= d0_next_pc_int;
pc_shadow_reg: PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN
d0_pc_int_0 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d0_pc_int_0 <= d0_next_pc_int;
END IF;
END IF;
END PROCESS;
pc_int <= d0_pc_int_0;
pcf <= pc_to_store;
d0check: IF ( DECODE_LATENCY /= 1 ) GENERATE
d0fail: ASSERT false REPORT "For LATENCY=1 DECODE_LATENCY is 1" SEVERITY Failure;
END GENERATE; -- error check
d0_explicit: IF (INFER_MEMORY = 0) GENERATE
altsyncram_component : altsyncram
GENERIC MAP
(
operation_mode => "ROM",
width_a => PCW_WIDTH,
widthad_a => PC_WIDTH,
numwords_a => PC_NUM_WORDS,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
address_aclr_a => "CLEAR0",
read_during_write_mode_mixed_ports => "DONT_CARE",
ram_block_type => "AUTO",
init_file => PROGRAM_FILE,
intended_device_family => "Stratix"
)
PORT MAP
(
clocken0 => ena_pc,
aclr0 => reset,
clock0 => clock,
address_a => pc_to_store,
q_a => pcw_from_store
);
pcw <= pcw_from_store;
END GENERATE; -- not INFER
END GENERATE; -- ALTERA LATENCY=1
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
d1: if ( LATENCY = 2) GENERATE
generate_next_pc_int : PROCESS (d1_pc_int_0, nextpc, load_pc)
BEGIN
IF ( load_pc = '1') THEN
d1_next_pc_int <= nextpc;
ELSE
d1_next_pc_int <= std_logic_vector(UNSIGNED( d1_pc_int_0) + 1);
END IF;
END PROCESS;
pc_to_store <= d1_next_pc_int;
d1check: IF ( DECODE_LATENCY /= 2 ) GENERATE
d1fail: ASSERT false REPORT "For LATENCY=2 DECODE_LATENCY is 2" SEVERITY Failure;
END GENERATE; -- error check
pc_shadow_reg_0: PROCESS (clock, reset) -- shadow of RAM input register
BEGIN
IF (reset = '1') THEN
d1_pc_int_0 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d1_pc_int_0 <= pc_to_store;
END IF;
END IF;
END PROCESS;
pc_shadow_reg_1: PROCESS (clock, reset) -- shadow or RAM output register
BEGIN
IF (reset = '1') THEN
d1_pc_int_1 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d1_pc_int_1 <= d1_pc_int_0;
END IF;
END IF;
END PROCESS;
pc_int <= d1_pc_int_1;
pcf <= pc_to_store;
d1_explicit: IF (INFER_MEMORY = 0) GENERATE
altsyncram_component : altsyncram
GENERIC MAP
(
operation_mode => "ROM",
width_a => PCW_WIDTH,
widthad_a => PC_WIDTH,
numwords_a => PC_NUM_WORDS,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
address_aclr_a => "CLEAR0",
read_during_write_mode_mixed_ports => "DONT_CARE",
ram_block_type => "AUTO",
init_file => PROGRAM_FILE,
intended_device_family => "Stratix"
)
PORT MAP (
clocken0 => ena_pc,
aclr0 => reset,
clock0 => clock,
address_a => pc_to_store,
q_a => pcw_from_store
);
pcw <= pcw_from_store;
END GENERATE; -- not INFER
END GENERATE; -- ALTERA LATENCY=2
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
d2: if ( LATENCY = 3) GENERATE
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_width => PC_WIDTH,
lpm_type => "LPM_COUNTER",
lpm_direction => "UP",
lpm_avalue => "0"
)
PORT MAP (
sload => load_pc,
clk_en => ena_pc,
clock => clock,
data => nextpc,
aset => reset,
q => pc_to_store
);
d2check: IF ( DECODE_LATENCY /= 2 ) GENERATE
d2fail: ASSERT false REPORT "For LATENCY=3 DECODE_LATENCY is 2" SEVERITY Failure;
END GENERATE; -- error check
pc_shadow_reg_0: PROCESS (clock, reset) -- shadow of RAM input register
BEGIN
IF (reset = '1') THEN
d2_pc_int_0 <= (OTHERS=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (ena_pc = '1') THEN
d2_pc_int_0 <= pc_to_store;
END IF;
END IF;
END PROCESS;
pc_shadow_reg_1: PROCESS (clock, reset) -- shadow or RAM output register
BEGIN
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