hopt_mult_l5.vqm

nios里面用自定义指令集来实现三角函数

wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[17]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[17] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[16]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[17] ;
wire \dffe2a[35] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab[0]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab[0] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[0] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[18] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[17]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[18] ;
wire \dffe2a[36] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[1] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[0]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[1] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[19] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[18]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[19] ;
wire \dffe2a[37] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[19] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[18]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[18] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[16] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[15]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[16]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[17]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[18]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[19]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[20] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[20] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[19]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[20] ;
wire \dffe2a[38] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[3] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab[2]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab[2] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[3] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[21] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[20]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[21] ;
wire \dffe2a[39] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[4] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[4] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[22] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[21]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[22] ;
wire \dffe2a[40] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[22]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[22] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[20]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[21]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[22]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[23] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[23] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[22]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[23] ;
wire \dffe2a[41] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT23 ;
wire \signa~combout ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|pre_sign_reg~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|pre_sign_reg ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|extension_bits[5] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab[11] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[5]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[5] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[6] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[24] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[23]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[24] ;
wire \dffe2a[42] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[7] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[25] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[24]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[25] ;
wire \dffe2a[43] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[8] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[26] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[25]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[26] ;
wire \dffe2a[44] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[9] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[27] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[26]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[27] ;
wire \dffe2a[45] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[10] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[28] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[27]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[28] ;
wire \dffe2a[46] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[11] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[11] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[29] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[28]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[29] ;
wire \dffe2a[47] ;
wire [5:0] \ded_mult_e4j1:ded_mult1|extension_bits ;
wire [29:0] \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg ;
wire [11:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result ;
wire [23:0] \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa ;
wire [23:0] \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result ;
wire [5:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|extension_bits ;
wire [29:0] \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg ;
wire [11:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa ;
wire [29:0] \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result ;
wire [11:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_datab ;
wire [47:0] dffe2a;


wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;


cycloneii_lcell_ff \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[1]~I (
	.clk(\clock0~clkctrl ),
	.datain(\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[1] ),
	.ena(\ena0~combout ),
	.regout(\ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[1] ));

cycloneii_lcell_ff \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[2]~I (
	.clk(\clock0~clkctrl ),
	.datain(\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[2] ),
	.ena(\ena0~combout ),
	.regout(\ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[2] ));

cycloneii_lcell_ff \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[3]~I (
	.clk(\clock0~clkctrl ),
	.datain(\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[3] ),
	.ena(\ena0~combout ),
	.regout(\ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[3] ));

cycloneii_lcell_ff \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[4]~I (
	.clk(\clock0~clkctrl ),
	.datain(\ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[4]~feeder ),