hopt_mult_l5.vqm

nios里面用自定义指令集来实现三角函数

wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[0]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[0] ;
wire \dffe2a[18]~feeder ;
wire \dffe2a[18] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[1] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[1] ;
wire \dffe2a[19] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[2] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[2] ;
wire \dffe2a[20]~feeder ;
wire \dffe2a[20] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[3]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[3] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[3] ;
wire \dffe2a[21] ;
wire \signb~combout ;
wire \datab[18]~combout ;
wire \datab[19]~combout ;
wire \datab[20]~combout ;
wire \datab[21]~combout ;
wire \datab[22]~combout ;
wire \datab[23]~combout ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[4] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[2]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[2] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[1]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[1] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[0] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[0]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[4] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[4] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[4] ;
wire \dffe2a[22] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[5] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[5] ;
wire \dffe2a[23] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[6]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[6] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[6] ;
wire \dffe2a[24] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[7] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[6]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[6] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[7] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[7] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[7] ;
wire \dffe2a[25] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[8] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[8] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[8] ;
wire \dffe2a[26] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[9]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[9] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[9] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[9] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[9] ;
wire \dffe2a[27] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[10]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[10] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[10] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[10] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[10] ;
wire \dffe2a[28] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[11]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[11] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[11] ;
wire \dffe2a[29] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[12] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[11]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[12] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[12] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[11]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[12] ;
wire \dffe2a[30] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[12]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[13] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[13] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[12]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[13] ;
wire \dffe2a[31] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[14]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[14] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[13]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[14] ;
wire \dffe2a[32] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[15]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[15] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[14]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[14] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[13]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[14]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[15] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[15] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[14]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[15] ;
wire \dffe2a[33] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[16] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[15]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[16] ;
wire \dffe2a[34] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT17 ;