hopt_mult_l5.vqm

nios里面用自定义指令集来实现三角函数

wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[13]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[20]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|substage_adder_dataa[21]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[0]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[2]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[6]~feeder ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|substage_adder_dataa[7]~feeder ;
wire \clock0~combout ;
wire \clock0~clkctrl ;
wire \ena0~combout ;
wire \~GND ;
wire \dataa[0]~combout ;
wire \dataa[1]~combout ;
wire \dataa[2]~combout ;
wire \dataa[3]~combout ;
wire \dataa[4]~combout ;
wire \dataa[5]~combout ;
wire \dataa[6]~combout ;
wire \dataa[7]~combout ;
wire \dataa[8]~combout ;
wire \dataa[9]~combout ;
wire \dataa[10]~combout ;
wire \dataa[11]~combout ;
wire \dataa[12]~combout ;
wire \dataa[13]~combout ;
wire \dataa[14]~combout ;
wire \dataa[15]~combout ;
wire \dataa[16]~combout ;
wire \dataa[17]~combout ;
wire \datab[0]~combout ;
wire \datab[1]~combout ;
wire \datab[2]~combout ;
wire \datab[3]~combout ;
wire \datab[4]~combout ;
wire \datab[5]~combout ;
wire \datab[6]~combout ;
wire \datab[7]~combout ;
wire \datab[8]~combout ;
wire \datab[9]~combout ;
wire \datab[10]~combout ;
wire \datab[11]~combout ;
wire \datab[12]~combout ;
wire \datab[13]~combout ;
wire \datab[14]~combout ;
wire \datab[15]~combout ;
wire \datab[16]~combout ;
wire \datab[17]~combout ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT24 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT25 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT26 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT27 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT28 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT29 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT30 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT31 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT32 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT33 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT34 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT35 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10 ;
wire \dffe2a[0]~feeder ;
wire \dffe2a[0] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT1 ;
wire \dffe2a[1]~feeder ;
wire \dffe2a[1] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT2 ;
wire \dffe2a[2]~feeder ;
wire \dffe2a[2] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT3 ;
wire \dffe2a[3]~feeder ;
wire \dffe2a[3] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT4 ;
wire \dffe2a[4] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT5 ;
wire \dffe2a[5]~feeder ;
wire \dffe2a[5] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT6 ;
wire \dffe2a[6]~feeder ;
wire \dffe2a[6] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT7 ;
wire \dffe2a[7]~feeder ;
wire \dffe2a[7] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT8 ;
wire \dffe2a[8]~feeder ;
wire \dffe2a[8] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT9 ;
wire \dffe2a[9]~feeder ;
wire \dffe2a[9] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT10 ;
wire \dffe2a[10] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT11 ;
wire \dffe2a[11]~feeder ;
wire \dffe2a[11] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT12 ;
wire \dffe2a[12]~feeder ;
wire \dffe2a[12] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT13 ;
wire \dffe2a[13]~feeder ;
wire \dffe2a[13] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT14 ;
wire \dffe2a[14]~feeder ;
wire \dffe2a[14] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT15 ;
wire \dffe2a[15] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT16 ;
wire \dffe2a[16] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT17 ;
wire \dffe2a[17]~feeder ;
wire \dffe2a[17] ;
wire \dataa[18]~combout ;
wire \dataa[19]~combout ;
wire \dataa[20]~combout ;
wire \dataa[21]~combout ;
wire \dataa[22]~combout ;
wire \dataa[23]~combout ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_mult5~23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6 ;