hopt_mult_l4.vqm

nios里面用自定义指令集来实现三角函数

wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_mult7~23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[0]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[2] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[2] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[2] ;
wire \dffe2a[20] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[3] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[3] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[3] ;
wire \dffe2a[21] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[4] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[4] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[4] ;
wire \dffe2a[22] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[5] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[5] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[5] ;
wire \dffe2a[23] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[6] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[6] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[6] ;
wire \dffe2a[24] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[7] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[7] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[7] ;
wire \dffe2a[25] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT26 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[8] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[8] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[8] ;
wire \dffe2a[26] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT27 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[9] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[9] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[9] ;
wire \dffe2a[27] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[10] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[10] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[10] ;
wire \dffe2a[28] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[11]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[11] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[11] ;
wire \dffe2a[29] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[12]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[12] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[11]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[12] ;
wire \dffe2a[30] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[13]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[13] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[12]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[13] ;
wire \dffe2a[31] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT32 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT31 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT30 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT29 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[11]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[12]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[13]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[14] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[14] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[13]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[14] ;
wire \dffe2a[32] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[15]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[15] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[14]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[15] ;
wire \dffe2a[33] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[16]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[16] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[15]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[16] ;
wire \dffe2a[34] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[17]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[17] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[16]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[17] ;
wire \dffe2a[35] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[0] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[18] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[17]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[18] ;
wire \dffe2a[36] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~10 ;