hopt_mult_l4.vqm

nios里面用自定义指令集来实现三角函数

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Internal Build 110 2/13/2005 SJ Full Version"

// DATE "02/16/2005 12:13:49"

module 	hopt_mult_l4 (
	clock0,
	ena0,
	dataa,
	datab,
	signa,
	signb,
	result);
input 	clock0;
input 	ena0;
input 	[23:0] dataa;
input 	[23:0] datab;
input 	signa;
input 	signb;
output 	[47:0] result;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT24 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT25 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT28 ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[0] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[1] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[2] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[3] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[4] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[5] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[6] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[7] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[8] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[9] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[10] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[11] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[12] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[13] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[14] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[15] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[16] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[17] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[18] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[19] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[20] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[21] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[22] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[23] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_datab_reg[29] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT22 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~0 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT12 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT13 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT14 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT15 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT16 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~0 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[0] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[1] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[11] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[12] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[13] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[15] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[16] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[17] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~0 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[18] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[19] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[2] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[3] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[22] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[5] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|signb_out_reg ;
wire \ded_mult_e4j1:ded_mult1|extension_bits[5] ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[2]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[4]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[6]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[9]~feeder ;
wire \ded_mult_e4j1:ded_mult1|substage_adder_dataa_reg[10]~feeder ;
wire \clock0~combout ;
wire \clock0~clkctrl ;
wire \ena0~combout ;
wire \~GND ;
wire \dataa[0]~combout ;
wire \dataa[1]~combout ;
wire \dataa[2]~combout ;
wire \dataa[3]~combout ;
wire \dataa[4]~combout ;
wire \dataa[5]~combout ;
wire \dataa[6]~combout ;
wire \dataa[7]~combout ;
wire \dataa[8]~combout ;
wire \dataa[9]~combout ;
wire \dataa[10]~combout ;
wire \dataa[11]~combout ;
wire \dataa[12]~combout ;
wire \dataa[13]~combout ;
wire \dataa[14]~combout ;