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📄 alt_cusp72_shift.vhd

📁 nios里面用自定义指令集来实现三角函数
💻 VHD
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-- Legal Notice: (C)2006 Altera Corporation. All rights reserved.  Your-- use of Altera Corporation's design tools, logic functions and other-- software and tools, and its AMPP partner logic functions, and any-- output files any of the foregoing (including device programming or-- simulation files), and any associated documentation or information are-- expressly subject to the terms and conditions of the Altera Program-- License Subscription Agreement or other applicable license agreement,-- including, without limitation, that your use is for the sole purpose-- of programming logic devices manufactured by Altera and sold by Altera-- or its authorized distributors.  Please refer to the applicable-- agreement for further details.LIBRARY IEEE, ALTERA;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;

USE altera.ALT_CUSP72_PACKAGE.ALL;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY alt_cusp72_shift IS
    GENERIC (
        NAME         : STRING := "";
        OPTIMIZED    : INTEGER := OPTIMIZED_ON;
        FAMILY       : INTEGER := FAMILY_STRATIX;
        DATA_WIDTH   : POSITIVE := 16;
        SHIFT_WIDTH  : POSITIVE := 4;
        LATENCY      : INTEGER := 0;
        MODE         : INTEGER := ALT_SHIFT_MODE_LOGICAL;
        DIRECTION    : INTEGER := ALT_SHIFT_DIREC_RIGHT
    );
    
    PORT (
        clock        : IN STD_LOGIC := '0';
        ena          : IN STD_LOGIC := '0';
        reset          : IN STD_LOGIC := '0';
        data         : IN  STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
        data_en      : IN STD_LOGIC := '1';
        shift        : IN STD_LOGIC_VECTOR(SHIFT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
        direc    : IN STD_LOGIC := '0';
        result       : OUT  STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
    );
END;
   
   
ARCHITECTURE SYN OF alt_cusp72_shift IS
    COMPONENT lpm_clshift
    GENERIC 
    (
        LPM_WIDTH      : POSITIVE := DATA_WIDTH;
        LPM_WIDTHDIST  : POSITIVE := SHIFT_WIDTH;
        LPM_SHIFTTYPE  : STRING := "LOGICAL";
        LPM_TYPE       : STRING := "LPM_CLSHIFT";
        LPM_HINT       : STRING := "UNUSED"
    );
    PORT 
    (
        data                 : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        distance             : IN STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 DOWNTO 0);
        direction            : IN STD_LOGIC := '0';
        result               : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        underflow, overflow  : OUT STD_LOGIC
    );
    END COMPONENT;

    SIGNAL data_int : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
    SIGNAL distance_int : STD_LOGIC_VECTOR(SHIFT_WIDTH-1 DOWNTO 0);
    SIGNAL direction_int : STD_LOGIC;
    SIGNAL result_int         : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
    SIGNAL ena_d1 : STD_LOGIC;
    SIGNAL data_en_d1 : STD_LOGIC;
BEGIN

    latencyX_gen : ASSERT (LATENCY > -1 AND LATENCY < 3) 
                   REPORT "Only 0, 1 or 2 clock cycle latencies are allowed on alt_cusp_shift" 
                   SEVERITY failure;

    latency_0_gen : IF LATENCY = 0 GENERATE
        data_int <= data;
        distance_int <= shift;
        direction_int <= direc;
        result <= result_int;
    END GENERATE;
    
    latency_1_gen : IF LATENCY = 1 GENERATE
        
        data_int <= data;
        distance_int <= shift;
        direction_int <= direc;
        
        r: PROCESS(clock, reset)
        BEGIN
            IF (reset = '1') THEN
                result <= (OTHERS=> '0');
            ELSIF clock'EVENT AND clock = '1' THEN
                IF (ena = '1' AND data_en = '1') THEN
                    result <= result_int;
                END IF;
            END IF;
        END PROCESS;
    END GENERATE;
    
    latency_2_gen : IF LATENCY = 2 GENERATE
        r: PROCESS(clock, reset)
        BEGIN
            IF (reset = '1') THEN
                data_int <= (OTHERS=> '0');
                direction_int <= '0';
                distance_int <= (OTHERS=> '0');
                result <= (OTHERS=> '0');
            ELSIF clock'EVENT AND clock = '1' THEN
                ena_d1 <= ena;
                data_en_d1 <= data_en;
                IF (ena = '1' AND data_en = '1') THEN
                    data_int <= data;
                    direction_int <= direc;
                    distance_int <= shift;    
                END IF;
                IF(ena_d1 = '1' AND data_en_d1 = '1') THEN
                    result <= result_int;
                END IF;
            END IF;
        END PROCESS;
    END GENERATE;
    

    shift_mode_logical_gen : IF MODE = ALT_SHIFT_MODE_LOGICAL GENERATE
        
        shift_mode_logical_both_gen : IF DIRECTION = ALT_SHIFT_DIREC_BOTH GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "LOGICAL"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => direction_int,
                    result => result_int
                );
        END GENERATE; -- shift_mode_logical_both_gen
        
        shift_mode_logical_left_gen : IF DIRECTION = ALT_SHIFT_DIREC_LEFT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "LOGICAL"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '0',
                    result => result_int
                );
        END GENERATE; -- shift_mode_logical_left_gen
        
        shift_mode_logical_right_gen : IF DIRECTION = ALT_SHIFT_DIREC_RIGHT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "LOGICAL"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '1',
                    result => result_int
                );
        END GENERATE; -- shift_mode_logical_right_gen
        
    END GENERATE; -- shift_mode_logical_gen
   
    shift_mode_arith_gen : IF MODE = ALT_SHIFT_MODE_ARITH GENERATE
    
        shift_mode_arith_both_gen : IF DIRECTION = ALT_SHIFT_DIREC_BOTH GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ARITHMETIC"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => direction_int,
                    result => result_int
                );
        END GENERATE; -- shift_mode_arith_both_gen
        
        shift_mode_arith_left_gen : IF DIRECTION = ALT_SHIFT_DIREC_LEFT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ARITHMETIC"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '0',
                    result => result_int
                );
        END GENERATE; -- shift_mode_arith_left_gen
        
        shift_mode_arith_right_gen : IF DIRECTION = ALT_SHIFT_DIREC_RIGHT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ARITHMETIC"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '1',
                    result => result_int
                );
        END GENERATE; -- shift_mode_arith_right_gen
        
    END GENERATE; -- shift_mode_arith_gen
    
    shift_mode_rotate_gen : IF MODE = ALT_SHIFT_MODE_ROTATE GENERATE
    
        shift_mode_rotate_both_gen : IF DIRECTION = ALT_SHIFT_DIREC_BOTH GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ROTATE"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => direction_int,
                    result => result_int
                );
        END GENERATE; -- shift_mode_rotate_both_gen
        
        shift_mode_rotate_left_gen : IF DIRECTION = ALT_SHIFT_DIREC_LEFT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ROTATE"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '0',
                    result => result_int
                );
        END GENERATE; -- shift_mode_rotate_left_gen
        
        shift_mode_rotate_right_gen : IF DIRECTION = ALT_SHIFT_DIREC_RIGHT GENERATE
            lpm_clshift_component : lpm_clshift
                GENERIC MAP 
                (
                    LPM_SHIFTTYPE => "ROTATE"
                )
                PORT MAP 
                (
                    data => data,
                    distance => distance_int,
                    direction => '1',
                    result => result_int
                );
        END GENERATE; -- shift_mode_rotate_right_gen
        
    END GENERATE; -- shift_mode_rotate_gen
END;

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