alt_cusp72_gpi.vhd

nios里面用自定义指令集来实现三角函数

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LIBRARY IEEE, ALTERA;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;

USE altera.ALT_CUSP72_PACKAGE.ALL;

ENTITY alt_cusp72_gpi IS
    GENERIC (
        NAME         : STRING := "";
        SIMULATION   : INTEGER := SIMULATION_OFF;
        OPTIMIZED    : INTEGER := OPTIMIZED_ON;
        FAMILY       : INTEGER := FAMILY_STRATIX;
        MODE         : STRING := "REGISTERED";
        WIDTH        : INTEGER := 16
    );
    PORT (
        clock : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        ena : IN STD_LOGIC := '1';
    
        gpio_in : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
        
        q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
        q_en: IN STD_LOGIC := '0';
        
        wait_change: IN STD_LOGIC := '0';
        wait_change_en: IN STD_LOGIC := '0';
        stall : OUT STD_LOGIC
    );
END;


ARCHITECTURE rtl OF alt_cusp72_gpi IS

  SIGNAL strobe : STD_LOGIC;
  SIGNAL out_val : STD_LOGIC_VECTOR ( WIDTH-1 DOWNTO 0);
  SIGNAL in_val : STD_LOGIC_VECTOR ( WIDTH-1 DOWNTO 0);

  SIGNAL last_in_val : STD_LOGIC_VECTOR ( WIDTH-1 DOWNTO 0);
  SIGNAL changed : STD_LOGIC;

BEGIN

--  -- synopsys synthesis_off
-- 
-- process 
--   variable rn : TTA_X_D_RN_T( 1 downto 0)  := 
--       ( 
--          new STRING'("in"), 
--          new STRING'("out") 
--       );
--   variable rv : TTA_X_D_RV_T( 1 downto 0)  := 
--       ( 
--           new STD_LOGIC_VECTOR(in_val'high downto in_val'low), 
--           new STD_LOGIC_VECTOR(out_val'high downto out_val'low) 
--       );
-- begin
-- 
--   loop
--     wait on in_val, out_val;
--     rv(1).all := in_val;
--     rv(0).all := out_val;
--     TTA_X_D_registerDump(NAME, rn, rv);
--   end loop;
--   --DEALLOCATE (rn(0));
--   --DEALLOCATE (rn(1));
--   --DEALLOCATE (rv(0));
--   --DEALLOCATE (rv(1));
-- end process;
--  -- synopsys synthesis_on

registered_gen : if MODE = "REGISTERED" generate

in_reg:  PROCESS (clock, reset)
  BEGIN
    IF (reset = '1') THEN
      in_val <= (others=> '0');
    ELSIF clock'EVENT AND clock = '1' THEN
        in_val <= gpio_in;
    END IF;
  END PROCESS;
  
end generate;

unregistered_gen : if MODE /= "REGISTERED" generate
  in_val_drive: in_val <= gpio_in;
end generate;

q_drive:  		 			q <= in_val;


process (clock, reset)
  BEGIN
    IF reset = '1' THEN
      last_in_val <= (others => '0');
      changed <= '0';
    ELSIF clock'EVENT AND clock = '1' THEN
      last_in_val <= in_val;
      IF (in_val /= last_in_val) THEN
        changed <= '1';
      ELSIF (q_en AND ena) = '1' THEN
        changed <= '0';
      END IF;
    END IF;
  END PROCESS;

stall <= wait_change AND wait_change_en AND (NOT changed);

END ;