hopt_mult_l3.vqm

nios里面用自定义指令集来实现三角函数

wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[12]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[13]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[14]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[15] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[14]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[15] ;
wire \dffe2a[33] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~DATAOUT34 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[15]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[16] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[15]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[16] ;
wire \dffe2a[34] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT17 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[16]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[17] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[16]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[17] ;
wire \dffe2a[35] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT18 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[17]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[18] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[17]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[18] ;
wire \dffe2a[36] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[18]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[19] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[18]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[19] ;
wire \dffe2a[37] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[19]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[20] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[19]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[20] ;
wire \dffe2a[38] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_pjj1:left_mult|mac_out8~DATAOUT21 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[20]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[21] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[20]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[21] ;
wire \dffe2a[39] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|add_sub_cella[21]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result[22] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[21]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[22] ;
wire \dffe2a[40] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT23 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT1 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT2 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT5 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~DATAOUT11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~6 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~7 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~8 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~9 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~10 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_mult3~11 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4~DATAOUT3 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT20 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_u2m1:right_mult|mac_out6~DATAOUT19 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|mac_out4 ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[0]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[1]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[2]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[3]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[4]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[5] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[22]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[23] ;
wire \dffe2a[41] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|signb_out_reg ;
wire \ded_mult_e4j1:ded_mult1|extension_bits[5] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[23]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[24] ;
wire \dffe2a[42] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[24]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[25] ;
wire \dffe2a[43] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[25]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[26] ;
wire \dffe2a[44] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[26]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[27] ;
wire \dffe2a[45] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[27]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[28] ;
wire \dffe2a[46] ;
wire \signa~combout ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|ded_mult_hho1:left_mult|pre_sign_reg ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|extension_bits[5] ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[5]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[6]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[7]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[8]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[9]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|add_sub_cella[10]~COUT ;
wire \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result[11] ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|add_sub_cella[28]~COUT ;
wire \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result[29] ;
wire \dffe2a[47] ;
wire [47:0] dffe2a;
wire [5:0] \ded_mult_e4j1:ded_mult1|extension_bits ;
wire [29:0] \ded_mult_e4j1:ded_mult1|add_sub_lqf:substage_adder|result ;
wire [23:0] \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|add_sub_nqf:substage_adder|result ;
wire [11:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|add_sub_kqf:substage_adder|result ;
wire [5:0] \ded_mult_e4j1:ded_mult1|ded_mult_0jo1:left_mult|extension_bits ;


wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;


cycloneii_mac_out \ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_out10~I (
	.clk(\clock0~clkctrl ),
	.aclr(gnd),
	.ena(\ena0~combout ),
	.dataa({\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT35 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT34 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT33 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT32 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT31 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT30 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT29 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT28 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT27 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT26 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT25 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT24 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT23 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT22 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT21 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT20 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT19 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT18 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT17 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT16 ,
\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT15 ,\ded_mult_e4j1:ded_mult1|ded_mult_e4m1:right_mult|ded_mult_f4i1:right_mult|mac_mult9~DATAOUT14 ,