fp_single_to_double.v

nios里面用自定义指令集来实现三角函数

module fp_single_to_double (
	clk,
	clk_en,
	reset,
	data_in,
	data_out
);

	input clk;
	input clk_en;
	input reset;
	input [31:0] data_in;

	wire [63:0] data_out;
	output [63:0] data_out;

	parameter ENABLE_OUTPUT_PIPELINING = "true";
	localparam EXPONENT_CONVERSION = 1023 - 127; // double precision are biased with 1023, single precision is biased by 127
	localparam MANTISSA_SHIFT_DISTANCE = 52 - 23;  // need to align the 23 bit mantissa (SP) to the upper bits of the 52 bit mantissa (DP)

	wire [10:0] new_exponent;
	wire [51:0] new_mantissa;
	wire new_sign_bit;
	wire [63:0] new_output;
	wire is_NaN;
	wire is_Inf;
	wire is_Denormal;

	// output pipeline signals
	wire [63:0] temp_output;
	reg [63:0] temp_output_d1;


	assign new_sign_bit = data_in[31];
	assign new_exponent = data_in[30:23] + EXPONENT_CONVERSION;
	assign new_mantissa = data_in[22:0] << MANTISSA_SHIFT_DISTANCE;
	assign new_output = {new_sign_bit, {new_exponent, new_mantissa}};

	assign is_NaN = (data_in[30:23] == 8'b11111111) & (data_in[22:0] != 0);
	assign is_Inf = (data_in[30:23] == 8'b11111111) & (data_in[22:0] == 0);
//	assign is_Denormal = (data_in[30:23] == 0) & (data_in[22:0] != 0);
	assign is_Denormal = (data_in[30:23] == 0);


	assign temp_output = (is_Inf == 1)? {new_sign_bit, 63'h7FF0000000000000} : // infinity is represented by the exponent maxed out and 0 mantissa
						 (is_NaN == 1)? {new_sign_bit, 63'h7FF8000000000000} : // NaN is represented by the exponent maxed out and non-zero mantisaa (setting the mantissa msb here) 
						 (is_Denormal == 1)? {new_sign_bit, 63'h0} : new_output;  // denormal in zero out, otherwise pass the properly formatted data out as the default case


	always @ (posedge clk)
	begin
		if(reset == 1)
		begin
			temp_output_d1 <= 0;
		end
		else
		begin
			if(clk_en == 1)
			begin
				temp_output_d1 <= temp_output;
			end
		end
	end


	generate  // when false the registered temp_ouptput will be optimized away
	if(ENABLE_OUTPUT_PIPELINING == "true")
	begin
		assign data_out = temp_output_d1;
	end
	else
	begin
		assign data_out = temp_output;
	end
	endgenerate


endmodule