📄 alt_cusp72_gpo.vhd
字号:
-- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your-- use of Altera Corporation's design tools, logic functions and other-- software and tools, and its AMPP partner logic functions, and any-- output files any of the foregoing (including device programming or-- simulation files), and any associated documentation or information are-- expressly subject to the terms and conditions of the Altera Program-- License Subscription Agreement or other applicable license agreement,-- including, without limitation, that your use is for the sole purpose-- of programming logic devices manufactured by Altera and sold by Altera-- or its authorized distributors. Please refer to the applicable-- agreement for further details.LIBRARY IEEE, ALTERA;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;
USE altera.ALT_CUSP72_PACKAGE.ALL;
ENTITY alt_cusp72_gpo IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '1';
enable_en : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
gpio_out : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END;
ARCHITECTURE rtl OF alt_cusp72_gpo IS
SIGNAL strobe : STD_LOGIC;
SIGNAL out_val : STD_LOGIC_VECTOR ( WIDTH-1 DOWNTO 0);
BEGIN
-- -- synopsys synthesis_off
--
-- process
-- variable rn : TTA_X_D_RN_T( 1 downto 0) :=
-- (
-- new STRING'("in"),
-- new STRING'("out")
-- );
-- variable rv : TTA_X_D_RV_T( 1 downto 0) :=
-- (
-- new STD_LOGIC_VECTOR(in_val'high downto in_val'low),
-- new STD_LOGIC_VECTOR(out_val'high downto out_val'low)
-- );
-- begin
--
-- loop
-- wait on in_val, out_val;
-- rv(1).all := in_val;
-- rv(0).all := out_val;
-- TTA_X_D_registerDump(NAME, rn, rv);
-- end loop;
-- --DEALLOCATE (rn(0));
-- --DEALLOCATE (rn(1));
-- --DEALLOCATE (rv(0));
-- --DEALLOCATE (rv(1));
-- end process;
-- -- synopsys synthesis_on
strobe <= enable and enable_en and ena;
registered_gen : if MODE = "REGISTERED" generate
out_reg: PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN
out_val <= (others=> '0');
ELSIF clock'EVENT AND clock = '1' THEN
IF (strobe = '1') THEN
out_val <= d;
END IF;
END IF;
END PROCESS;
end generate;
unregistered_gen : if MODE /= "REGISTERED" generate
out_val_drive: out_val <= d;
end generate;
gpio_out_drive: gpio_out <= out_val;
END ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -