spdp_cast_comp_top.v.bak

nios里面用自定义指令集来实现三角函数

    ((n == MCUSTOM_fmuls))? (8'h04) :
    ((n == MCUSTOM_fdivs))? (8'h08) :
    0;

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          OPCODE_reg <= 0;
      else if (clk_en & start & op_is_arithmetic)
          OPCODE_reg <= OPCODE_reg_mux;
      else if (clk_en & start & !op_is_arithmetic)
          OPCODE_reg <= (8'h20);
    end

  assign saw_my_start_mux = ((start))? 1 :
    (done)? 0 :
    saw_my_start;

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          saw_my_start <= 0;
      else if (clk_en)
          saw_my_start <= saw_my_start_mux;
    end

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          saw_my_start_plus_1 <= 0;
      else if (clk_en)
          saw_my_start_plus_1 <= saw_my_start;
    end

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          saw_my_start_plus_2 <= 0;
      else if (clk_en)
          saw_my_start_plus_2 <= saw_my_start_plus_1;
    end

  assign go_ci_mux = ((start & op_is_arithmetic) || (do_fixdu_subtract & !saw_go_ci))? 1 :
    ((go_ci & busy_gpo))? 0 :
    go_ci;

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          go_ci <= 0;
      else if (clk_en)
          go_ci <= go_ci_mux;
    end

  assign saw_go_ci_mux = ((go_ci))? 1 :
    (done)? 0 :
    saw_go_ci;

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          saw_go_ci <= 0;
      else if (clk_en)
          saw_go_ci <= saw_go_ci_mux;
    end

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          busy_gpo_plus_1 <= 0;
      else if (clk_en)
          busy_gpo_plus_1 <= busy_gpo;
    end

  always @(posedge clk or posedge reset)
    begin
      if (reset == 1)
          busy_gpo_plus_2 <= 0;
      else if (clk_en)
          busy_gpo_plus_2 <= busy_gpo_plus_1;
    end

  assign result = ((n == MCUSTOM_frdxhi))? X_reg[63 : 32] :
    ((n == MCUSTOM_frdxlo))? X_reg[31 : 0] :
    ((n == MCUSTOM_frdy))? Y_reg :
    ((n == MCUSTOM_FPU_ID))? {24'h526F64, 6'h00, dp_present_gpo, sp_present_gpo} :
    (op_is_arithmetic) ? (result_gpo[63 : 32]) :
	non_arithmetic_result;

  assign do_fixdu_subtract = (n == MCUSTOM_fixdu) && (saw_my_start) && (saw_my_start_plus_1) && (logical_ageb_result);

  assign op_is_logical = (n == MCUSTOM_fcmpned) || (n == MCUSTOM_fcmpeqd) || (n == MCUSTOM_fcmpged) || (n == MCUSTOM_fcmpgtd) || (n == MCUSTOM_fcmpled) || (n == MCUSTOM_fcmpltd);
  assign op_is_arithmetic = (n == MCUSTOM_faddd) || (n == MCUSTOM_fsubd) || (n == MCUSTOM_fmuld) || (n == MCUSTOM_fdivd) || (n == MCUSTOM_fadds) || (n == MCUSTOM_fsubs) || (n == MCUSTOM_fmuls) || (n == MCUSTOM_fdivs);
  assign op_is_register = (n == MCUSTOM_fwrx) || (n == MCUSTOM_fwry) || (n == MCUSTOM_frdxhi) || (n == MCUSTOM_frdxlo) || (n == MCUSTOM_frdy) || (n == MCUSTOM_FPU_ID);
  assign op_is_cast_int = (n == MCUSTOM_fixdu) || (n == MCUSTOM_fixdi) || (n == MCUSTOM_floatud) || (n == MCUSTOM_floatid);
  assign op_is_cast_fp = (n == MCUSTOM_ftruncds) || (n == MCUSTOM_fextsd);

  assign done = (op_is_register & saw_my_start) || 
				(op_is_logical & saw_my_start & saw_my_start_plus_1) || 
				(op_is_cast_fp & saw_my_start & saw_my_start_plus_1) || 
				(op_is_cast_int & saw_my_start & saw_my_start_plus_1 & saw_my_start_plus_2 & !do_fixdu_subtract) || 
				(op_is_cast_int & saw_my_start & saw_my_start_plus_1 & saw_my_start_plus_2 & do_fixdu_subtract & !go_ci & !busy_gpo & saw_go_ci & !busy_gpo_plus_1 & !busy_gpo_plus_2) || 
				(op_is_arithmetic & saw_my_start & !go_ci & !busy_gpo);

  SPDP_Engine the_SPDP_Engine
    (
      .busy_gpo (busy_gpo),
      .clock (clk),
      .double_a_reg_gpi ((op_is_arithmetic) ? (X_reg) : (DATA_reg)),
      .double_b_reg_gpi ((op_is_arithmetic) ? (DATA_reg) : (64'h41E0000000000000)),
      .dp_present_gpo (dp_present_gpo),
      .go_gpi (go_ci),
      .opcode_gpi (OPCODE_reg),
      .reset (reset),
      .result_gpo (result_gpo),
      .single_a_reg_gpi (DATA_reg[31 : 0]),
      .single_b_reg_gpi (DATA_reg[63 : 32]),
      .sp_present_gpo (sp_present_gpo)
    );

wire logical_aeb_result;
wire logical_agb_result;
wire logical_ageb_result;
wire logical_alb_result;
wire logical_aleb_result;
wire logical_aneb_result;
wire temp_logical_aeb_result;
wire temp_logical_agb_result;
wire temp_logical_ageb_result;
wire temp_logical_alb_result;
wire temp_logical_aleb_result;
wire temp_logical_aneb_result;
wire logical_unordered_result;

wire [31:0] double_to_single_result;
wire [63:0] single_to_double_result;
wire [31:0] float_to_int_result;
wire [63:0] int_to_float_result;

wire [31:0] non_arithmetic_result;
assign non_arithmetic_result = 	(n == MCUSTOM_ftruncds) ? (double_to_single_result) :
								(n == MCUSTOM_fextsd) ? (single_to_double_result[63:32]) :	// double result
								((n == MCUSTOM_fixdu) && (logical_ageb_result)) ? (float_to_int_result + 32'h80000000) :
								((n == MCUSTOM_fixdu) && (!logical_ageb_result)) ? (float_to_int_result) :
								(n == MCUSTOM_fixdi) ? (float_to_int_result) : 
								(n == MCUSTOM_floatud) ? (int_to_float_result[63:32]) :		// double result
								(n == MCUSTOM_floatid) ? (int_to_float_result[63:32]) :		// double result
								(n == MCUSTOM_fcmpned) ? (logical_aneb_result) : 
								(n == MCUSTOM_fcmpeqd) ? (logical_aeb_result) : 
								(n == MCUSTOM_fcmpged) ? (logical_ageb_result) : 
								(n == MCUSTOM_fcmpgtd) ? (logical_agb_result) : 
								(n == MCUSTOM_fcmpled) ? (logical_aleb_result) : 
								(n == MCUSTOM_fcmpltd) ? (logical_alb_result) :
								(0);
								
wire [31:0] non_arithmetic_result_Y;
assign non_arithmetic_result_Y =	(n == MCUSTOM_fextsd) ? (single_to_double_result[31:0]) :	// double result
									(n == MCUSTOM_floatud) ? (int_to_float_result[31:0]) :		// double result
									(n == MCUSTOM_floatid) ? (int_to_float_result[31:0]) :		// double result
									(0);

	// logical operator block
	altfp_compare the_altfp_compare (
		.aclr (reset),
		.aeb (temp_logical_aeb_result),
		.agb (temp_logical_agb_result),
		.ageb (temp_logical_ageb_result),
		.alb (temp_logical_alb_result),
		.aleb (temp_logical_aleb_result),
		.aneb (temp_logical_aneb_result),
		.clk_en (clk_en),
		.clock (clk),
		.dataa ((op_is_logical) ? (X_reg) : (DATA_reg)),
		.datab ((op_is_logical) ? (DATA_reg) : (64'h41E0000000000000)),
		.unordered (logical_unordered_result)
	);
	defparam the_altfp_compare.pipeline = 1;
	defparam the_altfp_compare.width_exp = 11;
	defparam the_altfp_compare.width_man = 52;
	defparam the_altfp_compare.lpm_type = "altfp_compare";

	assign logical_aeb_result = temp_logical_aeb_result & (~logical_unordered_result);
	assign logical_agb_result = temp_logical_agb_result & (~logical_unordered_result);
	assign logical_ageb_result = temp_logical_ageb_result & (~logical_unordered_result);
	assign logical_alb_result = temp_logical_alb_result & (~logical_unordered_result);
	assign logical_aleb_result = temp_logical_aleb_result & (~logical_unordered_result);
	assign logical_aneb_result = temp_logical_aneb_result & (~logical_unordered_result);

	// int/uint to float block (SP and DP)
	fp_int_to_float the_fp_int_to_float (
		.reset (reset),
		.clk (clk),
		.clk_en (clk_en),
		.input_data (DATA_reg[31:0]),
		.unsigned_operation ((n == MCUSTOM_floatud) ? (1) : (0)),
		.output_data (int_to_float_result)
	);
	defparam the_fp_int_to_float.ENABLE_INPUT_PIPELINING = "false";
	defparam the_fp_int_to_float.ENABLE_OUTPUT_PIPELINING = "false";
	defparam the_fp_int_to_float.ENABLE_INTERNAL_PIPELINING = "false";
	defparam the_fp_int_to_float.DATA_WIDTH = 32;
	defparam the_fp_int_to_float.EXPONENT_WIDTH = 11;
	defparam the_fp_int_to_float.MANTISSA_WIDTH = 52;

	// float to int/uint block (SP and DP)
	fp_float_to_int the_fp_float_to_int (
		.reset (reset),
		.clk (clk),
		.clk_en (clk_en),
		.operandA ((do_fixdu_subtract) ? (result_gpo) : (DATA_reg)),
		.result (float_to_int_result)
	);
	defparam the_fp_float_to_int.ENABLE_INPUT_PIPELINING = "false";
	defparam the_fp_float_to_int.ENABLE_OUTPUT_PIPELINING = "true";
	defparam the_fp_float_to_int.ENABLE_INTERNAL_PIPELINING = "true";
	defparam the_fp_float_to_int.EXPONENT_WIDTH = 11;
	defparam the_fp_float_to_int.MANTISSA_WIDTH = 52;

	// float to double block (DP mode only)
	fp_single_to_double the_fp_single_to_double (
		.clk (clk),
		.clk_en (clk_en),
		.reset (reset),
		.data_in (DATA_reg[31:0]),
		.data_out (single_to_double_result)
	);
	defparam the_fp_single_to_double.ENABLE_OUTPUT_PIPELINING = "true";

	// double to float block (DP mode only)
	fp_double_to_single the_fp_double_to_single (
		.clk (clk),
		.clk_en (clk_en),
		.reset (reset),
		.data_in (DATA_reg),
		.data_out (double_to_single_result)
	);
	defparam the_fp_double_to_single.ENABLE_OUTPUT_PIPELINING = "true";

endmodule