📄 viterbi_ber_hil.mdl
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Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Rounding
Operator "floor"
SampleTime "-1"
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "Viterbi_BER_HIL"
Location [114, 174, 1157, 816]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 212
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "93"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [987, 310, 1053, 365]
Orientation "down"
DropShadow on
NamePlacement "alternate"
SourceBlock "commchan3/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
seed "67"
noiseMode "Signal to noise ratio (Eb/No)"
EbNodB "EbNo"
EsNodB "10"
SNRdB "10"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
Ports [1, 1]
Position [715, 96, 790, 144]
DropShadow on
SourceBlock "commdigbbndpm2/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "Bernoulli Random\nBinary Generator"
Ports [0, 1]
Position [25, 98, 105, 142]
DropShadow on
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
P "0.5"
seed "435345"
Ts "1"
frameBased off
sampPerFrame "300"
orient off
outDataType "double"
}
Block {
BlockType Reference
Name "Convolutional \nEncoder"
Ports [1, 1]
Position [180, 95, 275, 145]
DropShadow on
SourceBlock "commcnvcod2/Convolutional\nEncoder"
SourceType "Convolutional Encoder"
trellis "poly2trellis(7, [133 171])"
reset "None"
}
Block {
BlockType Reference
Name "Decoded_bit"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [160, 537, 225, 553]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Output Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2]
Position [650, 477, 665, 653]
Orientation "left"
BackgroundColor "black"
ShowName off
Outputs "2"
DisplayOption "bar"
}
Block {
BlockType Reference
Name "Depuncturing"
Ports [1, 1]
Position [805, 551, 875, 579]
Orientation "left"
DropShadow on
SourceBlock "commsequence2/Insert Zero"
SourceType "Insert Zero"
insertZeroVector "comb_CA_CB'"
}
Block {
BlockType Display
Name "Display"
Ports [1]
Position [520, 311, 615, 379]
DropShadow on
Decimation "1"
}
Block {
BlockType Reference
Name "Error Rate Calculation"
Ports [2, 1]
Position [250, 319, 345, 366]
DropShadow on
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "4*tb_length + 29 + max(size(CA)) + 1024"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop on
numErr "maxNumErrs"
maxBits "maxNumBits"
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [595, 100, 650, 140]
DropShadow on
OutFrame "Frame based"
}
Block {
BlockType Reference
Name "HIL"
Ports [4, 1]
Position [240, 452, 470, 633]
Orientation "left"
SourceBlock "ALTELINK/AltLab/HIL"
SourceType "HardwareInTheLoopAlteraBlockSet"
InputCount "5"
InputNames "clock Pattern_CA Sample_1 Pattern_CB Sample_2"
InputWidth "1 1 3 1 3"
InputRepresentation "0 0 1 0 1"
InputExport "2 0 0 0 0"
InputFPP "0 0 0 0 0"
OutputCount "1"
OutputNames "Decoded_bit"
OutputWidth "1"
OutputRepresentation "0"
OutputExport "0"
OutputFPP "0"
JtagCable "2"
JtagDevice "1"
BurstMode on
BurstLength "1024"
FrameMode off
SOP "1"
OutValid "1"
QuartusProject "C:\\altera\\design_example\\Viterbi_BER\\Viterb"
"i_BER.qpf"
HilNewConfig off
ClockPinLocation "K17"
ClockPinSource "0"
HilDeviceOnBoard "EP2S60F1020C4ES"
DR_length "16"
dspbuilder_reset on
SLD_NODE_INFO "1019218008"
AssertSclrBeforeSimulation "1"
SampleTime "-1"
dspb_ver "5.1"
}
Block {
BlockType Reference
Name "Integer Delay"
Ports [1, 1]
Position [175, 238, 210, 272]
DropShadow on
SourceBlock "simulink/Discrete/Integer Delay"
SourceType "Integer Delay"
vinit "0.0"
samptime "-1"
NumDelays "4*tb_length + 29 + max(size(CA))+1024"
}
Block {
BlockType Scope
Name "MegaCore out vs reference"
Ports [2]
Position [380, 239, 455, 306]
DropShadow on
Location [-71, 338, 1132, 874]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "0~0"
YMax "1~1"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
MaxDataPoints "500"
}
Block {
BlockType Reference
Name "Pattern_CA"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [500, 467, 565, 483]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Pattern_CA"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER_HIL"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Pattern_CB"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [495, 557, 560, 573]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Pattern_CB"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER_HIL"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Puncture"
Ports [1, 1]
Position [460, 98, 540, 142]
DropShadow on
SourceBlock "commsequence2/Puncture"
SourceType "Puncture"
punctureVector "comb_CA_CB'"
}
Block {
BlockType Reference
Name "Sample_1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [495, 512, 560, 528]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "n_bits"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Sample_1"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER_HIL"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Sample_2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [495, 602, 560, 618]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "n_bits"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Sample_2"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER_HIL"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Signal From\nWorkspace"
Ports [0, 1]
Position [600, 463, 635, 487]
Orientation "left"
DropShadow on
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
X "CA"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace1"
Ports [0, 1]
Position [600, 553, 635, 577]
Orientation "left"
DropShadow on
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
X "CB"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType SubSystem
Name "Soft Output\nDemodulator"
Ports [1, 1]
Position [895, 543, 960, 587]
Orientation "left"
DropShadow on
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Soft Output\nDemodulator"
Location [223, 507, 969, 674]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [20, 43, 50, 57]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType ComplexToRealImag
Name "Complex to\nReal-Imag1"
Ports [1, 1]
Position [150, 35, 185, 65]
NamePlacement "alternate"
Output "Real"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [495, 33, 570, 67]
OutDataTypeMode "double"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain4"
Position [235, 35, 265, 65]
NamePlacement "alternate"
Gain "2^(n_bits-1)"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Rounding
Name "Rounding\nFunction"
Position [420, 35, 450, 65]
}
Block {
BlockType Saturate
Name "Saturation1"
Position [320, 35, 350, 65]
NamePlacement "alternate"
UpperLimit "2^(n_bits-1) - 0.00001"
LowerLimit "-2^(n_bits-1)"
LinearizeAsGain off
ZeroCross off
}
Block {
BlockType Outport
Name "Out1"
Position [610, 43, 640, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Rounding\nFunction"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Complex to\nReal-Imag1"
DstPort 1
}
Line {
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