viterbi_ber.mdl

this is viterbi algorithm

	  NamePlacement		  "alternate"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "puncturing_pattern_CA"
	  ppat			  "C:\\data\\Project\\dsp_builder\\error_corre"
"ction\\viterbi\\DSPBuilder_viterbi_system_demo"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "puncturing_pattern_CB"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [975, 57, 1040, 73]
	  Orientation		  "left"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "puncturing_pattern_CB"
	  ppat			  "C:\\data\\Project\\dsp_builder\\error_corre"
"ction\\viterbi\\DSPBuilder_viterbi_system_demo"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "receeived_samples_a"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [915, 147, 980, 163]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "n_bits"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "receeived_samples_a"
	  ppat			  "C:\\data\\Project\\dsp_builder\\error_corre"
"ction\\viterbi\\DSPBuilder_viterbi_system_demo"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "receeived_samples_b"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [915, 182, 980, 198]
	  Orientation		  "left"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "n_bits"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "receeived_samples_b"
	  ppat			  "C:\\data\\Project\\dsp_builder\\error_corre"
"ction\\viterbi\\DSPBuilder_viterbi_system_demo"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "viterbi"
	  Ports			  [11, 9]
	  Position		  [250, 51, 605, 569]
	  Orientation		  "left"
	  DropShadow		  on
	  NamePlacement		  "alternate"
	  SourceBlock		  "MegaCoreAltr/viterbi"
	  SourceType		  "HDLEntity AlteraBlockSet"
	  altr_type		  "altr_megacore"
	  flow_dir		  "C:\\software\\altera\\MegaCore\\viterbi-v4."
"2.3\\lib\\../../common/ip_toolbench/v1.2.7/bin"
	  core_dir		  "C:\\software\\altera\\MegaCore\\viterbi-v4."
"2.3\\lib\\ip_toolbench"
	  core_name		  "viterbi"
	  core_version		  "4.2.3"
	  vofile		  "DSPBuilder_Viterbi_BER\\viterbi.vo"
	  xmlmapfile		  "C:\\software\\altera\\DSPBuilder\\AltLib\\S"
"imgenCMap.xml"
	  wizard		  "viterbi"
	  NewVariation		  off
	  VhdlVariationName	  "viterbi.vhd"
	  VhdlVariationDate	  "10-Oct-2005 09:38:44"
	  n_input_port		  "11"
	  n_output_port		  "9"
	  array_input		  "eras_sym reset rr sink_dav_master sink_eop "
"sink_sop sink_val source_ena_slave tb_length tb_type tr_init_state "
	  array_output		  "bestadd bestmet decbit normalizations sink_"
"ena_master source_dav_slave source_eop source_sop source_val "
	  clockname		  "clk"
	  inptbwl		  "2 1 6 1 1 1 1 1 7 1 6 "
	  inptbwr		  " 0 0 0 0 0 0 0 0 0 0 0"
	  inptype		  "ububbbbbubu"
	  outptbwl		  "6 8 1 8 1 1 1 1 1 "
	  outptbwr		  "0 0 0 0 0 0 0 0 0"
	  outptype		  "uububbbbb"
	  dspbuilder_path	  "C:\\software\\altera\\DSPBuilder\\AltLib"
	  HDLInputPortsMappingAltera "eras_sym.2.0.u, reset.1.0.b, rr.6.0.u, s"
"ink_dav_master.1.0.b, sink_eop.1.0.b, sink_sop.1.0.b, sink_val.1.0.b, source_"
"ena_slave.1.0.b, tb_length.7.0.u, tb_type.1.0.b, tr_init_state.6.0.u"
	  HDLOutputPortsMappingAltera "bestadd.6.0.u, bestmet.8.0.u, decbit.1."
"0.b, normalizations.8.0.u, sink_ena_master.1.0.b, source_dav_slave.1.0.b, sou"
"rce_eop.1.0.b, source_sop.1.0.b, source_val.1.0.b"
	  HDLImplicitPortsMappingAltera	"clk.clock"
	  HDLParameterMappingAltera "NOHDLPARAMETER"
	  HDLLibraryInformationAltera "ADD_COMPONENT_SECTION"
	  HDLComponentNameAltera  "viterbi"
	  HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_Viterbi_BER/vite"
"rbi_add.tcl\";"
	}
	Block {
	  BlockType		  Outport
	  Name			  "decoded"
	  Position		  [85, 193, 115, 207]
	  Orientation		  "left"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "receeived_samples_b"
	  SrcPort		  1
	  DstBlock		  "Delay1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "receeived_samples_a"
	  SrcPort		  1
	  DstBlock		  "Delay2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Single Pulse 2"
	  SrcPort		  1
	  Points		  [0, 25]
	  DstBlock		  "viterbi"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "BusConcatenation"
	  SrcPort		  1
	  DstBlock		  "viterbi"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Single Pulse 1"
	  SrcPort		  1
	  DstBlock		  "Delay"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  2
	  DstBlock		  "Terminator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  1
	  DstBlock		  "Terminator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  4
	  DstBlock		  "Terminator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "viterbi"
	  DstPort		  11
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "viterbi"
	  DstPort		  9
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  3
	  DstBlock		  "decoded_bit"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "symbol_a"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "receeived_samples_a"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "symbol_b"
	  SrcPort		  1
	  DstBlock		  "receeived_samples_b"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "decoded_bit"
	  SrcPort		  1
	  DstBlock		  "decoded"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  5
	  Points		  [-60, 0; 0, 80]
	  DstBlock		  "Atlantic outputs"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  6
	  Points		  [-45, 0; 0, 40]
	  DstBlock		  "Atlantic outputs"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  7
	  DstBlock		  "Atlantic outputs"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  8
	  Points		  [-45, 0; 0, -40]
	  DstBlock		  "Atlantic outputs"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "viterbi"
	  SrcPort		  9
	  Points		  [-60, 0; 0, -80]
	  DstBlock		  "Atlantic outputs"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "BusConcatenation1"
	  SrcPort		  1
	  Points		  [-60, 0; 0, 35]
	  DstBlock		  "viterbi"
	  DstPort		  1
	}
	Line {
	  Name			  "symbol_B"
	  Labels		  [0, 0]
	  SrcBlock		  "Delay1"
	  SrcPort		  1
	  DstBlock		  "BusConcatenation"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "puncturing_pattern_CA"
	  SrcPort		  1
	  DstBlock		  "NOT"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "puncturing_pattern_CB"
	  SrcPort		  1
	  DstBlock		  "NOT1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "CA"
	  SrcPort		  1
	  DstBlock		  "puncturing_pattern_CA"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "CB"
	  SrcPort		  1
	  DstBlock		  "puncturing_pattern_CB"
	  DstPort		  1
	}
	Line {
	  Name			  "symbol_A"
	  Labels		  [1, 0]
	  SrcBlock		  "Delay2"
	  SrcPort		  1
	  DstBlock		  "BusConcatenation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "GND"
	  SrcPort		  1
	  Points		  [-75, 0]
	  Branch {
	    DstBlock		    "viterbi"
	    DstPort		    10
	  }
	  Branch {
	    Points		    [0, -225]
	    DstBlock		    "viterbi"
	    DstPort		    5
	  }
	}
	Line {
	  SrcBlock		  "VCC"
	  SrcPort		  1
	  Points		  [-70, 0]
	  Branch {
	    DstBlock		    "viterbi"
	    DstPort		    8
	  }
	  Branch {
	    Points		    [0, -45]
	    Branch {
	      Points		      [0, -135]
	      DstBlock		      "viterbi"
	      DstPort		      4
	    }
	    Branch {
	      DstBlock		      "viterbi"
	      DstPort		      7
	    }
	  }
	}
	Line {
	  Name			  "sink_sop"
	  Labels		  [0, 0]
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  DstBlock		  "viterbi"
	  DstPort		  6
	}
	Line {
	  SrcBlock		  "Delay3"
	  SrcPort		  1
	  DstBlock		  "BusConcatenation1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay4"
	  SrcPort		  1
	  DstBlock		  "BusConcatenation1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "NOT"
	  SrcPort		  1
	  DstBlock		  "Delay3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "NOT1"
	  SrcPort		  1
	  DstBlock		  "Delay4"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "background1"
      Ports		      []
      Position		      [178, 211, 676, 401]
      Orientation	      "left"
      BackgroundColor	      "[0.929412, 0.913725, 0.572549]"
      DropShadow	      on
      ShowName		      off
      ShowPortLabels	      off
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "disp('')\n\n"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"background1"
	Location		[602, 355, 797, 437]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "background2"
      Ports		      []
      Position		      [178, 60, 858, 191]
      Orientation	      "left"
      BackgroundColor	      "[0.984314, 0.709804, 0.666667]"
      DropShadow	      on
      ShowName		      off
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "disp('')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"background2"
	Location		[602, 355, 797, 437]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "background3"
      Ports		      []
      Position		      [183, 425, 969, 628]
      Orientation	      "left"
      BackgroundColor	      "[0.623529, 0.874510, 0.862745]"
      DropShadow	      on
      ShowName		      off
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "disp('')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"background3"
	Location		[2,