📄 viterbi_ber.mdl
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ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 43, 55, 57]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Buffer"
Ports [1, 1]
Position [80, 25, 130, 75]
SourceBlock "dspbuff3/Buffer"
SourceType "Buffer"
N "max(size(CA))"
V "0"
ic "0"
}
Block {
BlockType Reference
Name "Convert 2-D to 1-D"
Ports [1, 1]
Position [265, 29, 295, 71]
SourceBlock "dspsigattribs/Convert 2-D to 1-D"
SourceType "Convert 2-D to 1-D"
ShowPortLabels off
}
Block {
BlockType Reference
Name "Transpose"
Ports [1, 1]
Position [165, 30, 220, 70]
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
Hermitian off
overflowFlag on
}
Block {
BlockType Outport
Name "Out1"
Position [320, 43, 350, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Buffer"
SrcPort 1
Points [0, 0]
DstBlock "Transpose"
DstPort 1
}
Line {
SrcBlock "Transpose"
SrcPort 1
DstBlock "Convert 2-D to 1-D"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0]
DstBlock "Buffer"
DstPort 1
}
Line {
SrcBlock "Convert 2-D to 1-D"
SrcPort 1
Points [0, 0]
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Viterbi_MegaCore_wrapper"
Ports [4, 1]
Position [290, 447, 435, 603]
Orientation "left"
AncestorBlock "ALTELINK/AltLab/HDL SubSystem"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskType "SubSystem AlteraBlockSet"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Viterbi_MegaCore_wrapper"
Location [-4, 303, 1103, 981]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "symbol_a"
Position [1050, 148, 1080, 162]
Orientation "left"
NamePlacement "alternate"
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "symbol_b"
Position [1050, 183, 1080, 197]
Orientation "left"
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "CA"
Position [1070, 28, 1100, 42]
Orientation "left"
NamePlacement "alternate"
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "CB"
Position [1070, 58, 1100, 72]
Orientation "left"
Port "4"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Scope
Name "Atlantic outputs"
Ports [5]
Position [75, 380, 105, 460]
Orientation "left"
NamePlacement "alternate"
Location [188, 390, 512, 629]
Open off
NumInputPorts "5"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
axes4 "%<SignalLabel>"
axes5 "%<SignalLabel>"
}
YMin "-5~-5~-5~-5~-5"
YMax "5~5~5~5~5"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "BusConcatenation"
Ports [2, 1]
Position [645, 137, 715, 208]
Orientation "left"
NamePlacement "alternate"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "n_bits"
bwr "n_bits"
blean off
}
Block {
BlockType Reference
Name "BusConcatenation1"
Ports [2, 1]
Position [690, 20, 760, 80]
Orientation "left"
NamePlacement "alternate"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "1"
bwr "1"
blean off
}
Block {
BlockType Reference
Name "Constant1"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [710, 436, 760, 454]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "7"
bwr "0"
sat off
rnd off
bp off
mask_cst "tb_length"
ncstsamp "1"
cst "105"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Constant2"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [710, 526, 760, 544]
Orientation "left"
NamePlacement "alternate"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "1"
cst "0"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [715, 290, 745, 330]
Orientation "left"
NamePlacement "alternate"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
Port {
PortNumber 1
Name "sink_sop"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [765, 170, 795, 210]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
Port {
PortNumber 1
Name "symbol_B"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [820, 135, 850, 175]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
Port {
PortNumber 1
Name "symbol_A"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Delay3"
Ports [1, 1]
Position [835, 15, 865, 55]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay4"
Ports [1, 1]
Position [790, 45, 820, 85]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "GND"
Ports [0, 1]
Position [715, 481, 730, 499]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "bus_alteradspbuilder/GND"
SourceType "SGND AlteraBlockSet"
ncstsamp "1"
}
Block {
BlockType Reference
Name "NOT"
Ports [1, 1]
Position [915, 27, 955, 43]
Orientation "left"
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "NOT1"
Ports [1, 1]
Position [890, 57, 930, 73]
Orientation "left"
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "Single Pulse 1"
Ports [0, 1]
Position [780, 302, 855, 318]
Orientation "left"
NamePlacement "alternate"
SourceBlock "gate_alteradspbuilder/Single Pulse "
SourceType "HDLEntity AlteraBlockSet"
SignalGenerationType "Step (1 to 0)"
UseControlInputs off
Impulsewidth "1"
Impulsedelay "1"
StepDelay "1"
ntsamp "1"
HDLInputPortsMappingAltera "NOINPUT"
HDLOutputPortsMappingAltera "q.1.0.b"
HDLImplicitPortsMappingAltera "clock.clock, ena.VCC, sclr.sclr"
HDLParameterMappingAltera "StepDelay.1.natural,direction.0.natural"
HDLLibraryInformationAltera "library dspbuilder;use dspbuilder.dspbu"
"ilderblock.all;"
HDLComponentNameAltera "sStepAltr"
}
Block {
BlockType Reference
Name "Single Pulse 2"
Ports [0, 1]
Position [630, 97, 705, 113]
Orientation "left"
NamePlacement "alternate"
SourceBlock "gate_alteradspbuilder/Single Pulse "
SourceType "HDLEntity AlteraBlockSet"
SignalGenerationType "Step (1 to 0)"
UseControlInputs off
Impulsewidth "1"
Impulsedelay "1"
StepDelay "1"
ntsamp "1"
HDLInputPortsMappingAltera "NOINPUT"
HDLOutputPortsMappingAltera "q.1.0.b"
HDLImplicitPortsMappingAltera "clock.clock, ena.VCC, sclr.sclr"
HDLParameterMappingAltera "StepDelay.1.natural,direction.0.natural"
HDLLibraryInformationAltera "library dspbuilder;use dspbuilder.dspbu"
"ilderblock.all;"
HDLComponentNameAltera "sStepAltr"
}
Block {
BlockType Terminator
Name "Terminator"
Position [185, 80, 205, 100]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Terminator
Name "Terminator1"
Position [185, 135, 205, 155]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Terminator
Name "Terminator2"
Position [175, 245, 195, 265]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Reference
Name "VCC"
Ports [0, 1]
Position [715, 392, 730, 408]
Orientation "left"
ShowName off
SourceBlock "bus_alteradspbuilder/VCC"
SourceType "SVCC AlteraBlockSet"
ncstsamp "1"
}
Block {
BlockType Reference
Name "decoded_bit"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [140, 192, 205, 208]
Orientation "left"
NamePlacement "alternate"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Output Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
}
Block {
BlockType Reference
Name "puncturing_pattern_CA"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [975, 27, 1040, 43]
Orientation "left"
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