📄 viterbi_ber.mdl
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subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop on
numErr "maxNumErrs"
maxBits "maxNumBits"
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [645, 100, 700, 140]
DropShadow on
OutFrame "Frame based"
}
Block {
BlockType Reference
Name "Integer Delay"
Ports [1, 1]
Position [205, 223, 240, 257]
DropShadow on
SourceBlock "simulink/Discrete/Integer Delay"
SourceType "Integer Delay"
vinit "0.0"
samptime "-1"
NumDelays "4*tb_length + 29 + max(size(CA))"
}
Block {
BlockType Scope
Name "MegaCore out vs reference"
Ports [2]
Position [430, 219, 510, 301]
DropShadow on
Location [6, 338, 1209, 874]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "0~0"
YMax "1~1"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
MaxDataPoints "500"
}
Block {
BlockType Reference
Name "Pattern_CA"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [470, 537, 535, 553]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Pattern_CA"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER"
nSgCpl "1"
}
Block {
BlockType Reference
Name "Pattern_CB"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [470, 577, 535, 593]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Pattern_CB"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER"
nSgCpl "1"
}
Block {
BlockType Reference
Name "Puncture"
Ports [1, 1]
Position [505, 98, 585, 142]
DropShadow on
SourceBlock "commsequence2/Puncture"
SourceType "Puncture"
punctureVector "comb_CA_CB'"
}
Block {
BlockType "S-Function"
Name "Sample_1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [465, 457, 530, 473]
Orientation "left"
FunctionName "SSbfIn"
Parameters "-1 bwl bwr ppat 0 0 bp 1 0 0 modulename nSgCpl "
"sgn"
MaskType "AltBus AlteraBlockSet"
MaskDescription "Input Port \n\nCasts a signal to a bus.\n\nUsag"
"e: \n\n1. Choose the bus type you wish to use and click Apply. Different opti"
"ons\n are available for each bus type.\n2. Make additional settings as nee"
"ded.\n3. Click OK."
MaskHelp "helpview(blocklookup(gcb))"
MaskPromptString "Bus Type |Node Type "
" |[number of bits].[] |[].[number of bits] |Satu"
"rate|Round|Bypass Bus Format|Constant Value|Pin Location|Calc ConstVal|module"
"name|ppat|nSgCpl "
MaskStyleString "popup(Signed Integer|Signed Fractional|Unsigned"
" Integer|Single Bit),popup(Input Port),edit,edit,checkbox,checkbox,checkbox,e"
"dit,edit,edit,edit,edit,edit"
MaskTunableValueString "off,off,off,off,off,off,off,off,off,off,off,off"
",off"
MaskCallbackString "SInputAltr_Init(gcb);|SInputAltr_Init(gcb);||||"
"|||||||"
MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on"
MaskVisibilityString "on,off,on,off,off,off,off,off,off,off,off,off,o"
"ff"
MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on"
MaskVarAliasString ",,,,,,,,,,,,"
MaskVariables "sgn=@1;nodetype=@2;bwl=@3;bwr=@4;sat=@5;rnd=@6;"
"bp=@7;mask_cst=@8;LocPin=@9;cst=@10;modulename=&11;ppat=&12;nSgCpl=@13;"
MaskInitialization "SInputAltr_Init(gcb);\n\n\n"
MaskDisplay "disp('i2:0');plot([0 10 40 50 40 10 0 10 14 4 "
"14 36 46 36], [10 0 0 10 20 20 10 0 0 10 20 20 10 0]);"
MaskSelfModifiable on
MaskIconFrame off
MaskIconOpaque on
MaskIconRotate "port"
MaskIconUnits "autoscale"
MaskValueString "Signed Integer|Input Port|n_bits|0|off|off|off|"
"0|any|0|Sample_1|C:\\altera\\design_example\\Viterbi_BER\\DSPBuilder_Viterbi_"
"BER|1"
MaskTabNameString ",,,,,,,,,,,,"
}
Block {
BlockType Reference
Name "Sample_2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [465, 497, 530, 513]
Orientation "left"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "n_bits"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Sample_2"
ppat "C:\\altera\\design_example\\Viterbi_BER\\DSPBui"
"lder_Viterbi_BER"
nSgCpl "1"
}
Block {
BlockType Reference
Name "Signal From\nWorkspace"
Ports [0, 1]
Position [585, 533, 620, 557]
Orientation "left"
DropShadow on
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
X "CA"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace1"
Ports [0, 1]
Position [585, 573, 620, 597]
Orientation "left"
DropShadow on
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
X "CB"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [19, 243, 88, 290]
ForegroundColor "blue"
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix II"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "C:\\altera\\design_example\\Viterbi_BER"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation on
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType SubSystem
Name "Soft Output\nDemodulator"
Ports [1, 1]
Position [870, 463, 935, 507]
Orientation "left"
DropShadow on
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Soft Output\nDemodulator"
Location [223, 507, 969, 674]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [20, 43, 50, 57]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType ComplexToRealImag
Name "Complex to\nReal-Imag1"
Ports [1, 1]
Position [150, 35, 185, 65]
NamePlacement "alternate"
Output "Real"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [495, 33, 570, 67]
OutDataTypeMode "double"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain4"
Position [235, 35, 265, 65]
NamePlacement "alternate"
Gain "2^(n_bits-1)"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Rounding
Name "Rounding\nFunction"
Position [420, 35, 450, 65]
}
Block {
BlockType Saturate
Name "Saturation1"
Position [320, 35, 350, 65]
NamePlacement "alternate"
UpperLimit "2^(n_bits-1) - 0.00001"
LowerLimit "-2^(n_bits-1)"
LinearizeAsGain off
ZeroCross off
}
Block {
BlockType Outport
Name "Out1"
Position [610, 43, 640, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Rounding\nFunction"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Complex to\nReal-Imag1"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Saturation1"
SrcPort 1
DstBlock "Rounding\nFunction"
DstPort 1
}
Line {
SrcBlock "Gain4"
SrcPort 1
DstBlock "Saturation1"
DstPort 1
}
Line {
SrcBlock "Complex to\nReal-Imag1"
SrcPort 1
DstBlock "Gain4"
DstPort 1
}
}
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [420, 345, 530, 375]
DropShadow on
VariableName "ber__n_errors__n_bits"
MaxDataPoints "1"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType SubSystem
Name "To_Viterbi_Decoder"
Ports [1, 1]
Position [650, 458, 735, 512]
Orientation "left"
DropShadow on
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "To_Viterbi_Decoder"
Location [604, 637, 909, 739]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [250, 43, 280, 57]
Orientation "left"
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Buffer"
Ports [1, 1]
Position [175, 25, 225, 75]
Orientation "left"
SourceBlock "dspbuff3/Buffer"
SourceType "Buffer"
N "2"
V "0"
ic "0"
}
Block {
BlockType Reference
Name "Convert 1-D to 2-D"
Ports [1, 1]
Position [80, 39, 125, 61]
Orientation "left"
SourceBlock "dspsigattribs/Convert 1-D to 2-D"
SourceType "Convert 1-D to 2-D"
ShowPortLabels off
M "1"
N "2"
frameBasedOut off
}
Block {
BlockType Outport
Name "Out1"
Position [25, 43, 55, 57]
Orientation "left"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Buffer"
SrcPort 1
DstBlock "Convert 1-D to 2-D"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0]
DstBlock "Buffer"
DstPort 1
}
Line {
SrcBlock "Convert 1-D to 2-D"
SrcPort 1
Points [0, 0]
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "To_frame_for_puncturing"
Ports [1, 1]
Position [365, 95, 440, 145]
DropShadow on
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "To_frame_for_puncturing"
Location [301, 495, 676, 597]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
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