mac_mcu.s51

来自「TI的基于ZIGBEE2006的协议栈」· S51 代码 · 共 1,611 行 · 第 1/5 页

//   85  *  used to enable and disable interrupts and must be set independently of the lower four bits.
//   86  *  Since the original value of the lower four bits is lost (it reads as something else) these
//   87  *  bits must be stored in a shadow variable.  This shadow variable is declared here and is
//   88  *  used where needed in this module.
//   89  */

        RSEG XDATA_Z:XDATA:NOROOT(0)
        REQUIRE __INIT_XDATA_Z
//   90 static uint8 shadowPerof2;
??shadowPerof2:
        DS 1
//   91 
//   92 
//   93 /* ------------------------------------------------------------------------------------------------
//   94  *                                       Local Prototypes
//   95  * ------------------------------------------------------------------------------------------------
//   96  */
//   97 static void mcuRecordMaxRssiIsr(void);
//   98 
//   99 
//  100 /**************************************************************************************************
//  101  * @fn          macMcuInit
//  102  *
//  103  * @brief       Initialize the MCU.
//  104  *
//  105  * @param       none
//  106  *
//  107  * @return      none
//  108  **************************************************************************************************
//  109  */

        RSEG BANKED_CODE:CODE:NOROOT(0)
//  110 void macMcuInit(void)
macMcuInit:
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function macMcuInit
//  111 {
        FUNCALL macMcuInit, halAssertHandler
        LOCFRAME ISTACK, 2, STACK
        ARGFRAME ISTACK, 2, STACK
        FUNCALL macMcuInit, halAssertHandler
        LOCFRAME ISTACK, 2, STACK
        ARGFRAME ISTACK, 2, STACK
        FUNCALL macMcuInit, macRxOn
        LOCFRAME ISTACK, 2, STACK
        ARGFRAME ISTACK, 2, STACK
        FUNCALL macMcuInit, macRxOff
        LOCFRAME ISTACK, 2, STACK
        ARGFRAME ISTACK, 2, STACK
        PUSH	DPL
        CFI DPL0 Frame(CFA_SP, 4)
        CFI CFA_SP SP+-4
        PUSH	DPH
        CFI DPH0 Frame(CFA_SP, 5)
        CFI CFA_SP SP+-5
        ; Saved register size: 2
        ; Auto size: 0
//  112   uint16 i;
//  113 
//  114   MAC_ASSERT(CHVER != 0x00); /* chip version A is obsolete */
        MOV	DPTR,#-0x20a0
        MOVX	A,@DPTR
        JNZ	??macMcuInit_0
        ; Setup parameters for call to function halAssertHandler
        MOV	DPTR,#(halAssertHandler & 0xffff)
        MOV	A,#((halAssertHandler >> 16) & 0xff)
        LCALL	?BCALL               ; Banked call to: DPTR()
//  115 ///////////////////////////////////////////////////////////////////////////////////
//  116 //  REV_B_WORKAROUND : replace with line below when Rev B is obsoleted
//  117 #ifndef _REMOVE_REV_B_WORKAROUNDS
//  118 #else
//  119 //vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
//  120 //  keep this code, delete the rest
//  121   MAC_ASSERT(CHVER != 0x01); /* chip version B is obsolete */
//  122 //^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
//  123 #endif
//  124 ///////////////////////////////////////////////////////////////////////////////////
//  125   MAC_ASSERT(CHVER != 0x02); /* chip version C is obsolete */
??macMcuInit_0:
        MOV	DPTR,#-0x20a0
        MOVX	A,@DPTR
        XRL	A,#0x2
        JNZ	??macMcuInit_1
        ; Setup parameters for call to function halAssertHandler
        MOV	DPTR,#(halAssertHandler & 0xffff)
        MOV	A,#((halAssertHandler >> 16) & 0xff)
        LCALL	?BCALL               ; Banked call to: DPTR()
//  126 
//  127 ///////////////////////////////////////////////////////////////////////////////////
//  128 //  REV_B_WORKAROUND : workaround for chip bug #51, remove when fixed
//  129 #ifndef _REMOVE_REV_B_WORKAROUNDS
//  130   FSCTRLH = 0x41;
??macMcuInit_1:
        MOV	A,#0x41
        MOV	DPTR,#-0x20f0
        MOVX	@DPTR,A
//  131   FSTST1L = 0x32;
        MOV	A,#0x32
        MOV	DPTR,#-0x20cf
        MOVX	@DPTR,A
//  132   FSTST2H = 0x20;
        MOV	A,#0x20
        MOV	DPTR,#-0x20ce
        MOVX	@DPTR,A
//  133 #endif
//  134 ///////////////////////////////////////////////////////////////////////////////////
//  135 
//  136 ///////////////////////////////////////////////////////////////////////////////////
//  137 //  REV_B_WORKAROUND : workaround for chip bug #267, remove when fixed
//  138 #ifndef _REMOVE_REV_B_WORKAROUNDS
//  139   MDMCTRL0L |= AUTOACK;  /* enable autoack */
        MOV	DPTR,#-0x20fd
        MOVX	A,@DPTR
        SETB	0xE0 /* A   */.4
        MOVX	@DPTR,A
//  140 #endif
//  141 ///////////////////////////////////////////////////////////////////////////////////
//  142 
//  143   /* tuning adjustments for optimal radio performance; details available in datasheet */
//  144   RXCTRL0H = 0x32;
        MOV	A,#0x32
        MOV	DPTR,#-0x20f4
        MOVX	@DPTR,A
//  145   RXCTRL0L = 0xF5;
        MOV	A,#-0xb
        MOV	DPTR,#-0x20f3
        MOVX	@DPTR,A
//  146  
//  147 ///////////////////////////////////////////////////////////////////////////////////
//  148 //  REV_B_WORKAROUND : workaround for chip bug #267, update when fixed
//  149 #ifndef _REMOVE_REV_B_WORKAROUNDS
//  150   /* do nothing */
//  151 #else
//  152 // this part can go away once new .h file is shipping
//  153 #ifndef IRQSRC
//  154 #define IRQSRC    XREG( 0xDF64 )
//  155 #endif
//  156 //vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
//  157 //  keep this code, delete the rest
//  158   /* enable TX_DONE interrupts for ACK transmits */
//  159   IRQSRC = TXACK;
//  160 //^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
//  161 #endif
//  162 ///////////////////////////////////////////////////////////////////////////////////
//  163 
//  164   /* disable the CSPT register compare function */
//  165   CSPT = 0xFF;
        MOV	A,#-0x1
        MOV	DPTR,#-0x20ea
        MOVX	@DPTR,A
//  166 
//  167   /* enable general RF interrupts */
//  168   IEN2 |= RFIE;
        ORL	0x9a,#0x1
//  169 
//  170   /* intialize shadow register */
//  171   shadowPerof2 = 0;
        CLR	A
        MOV	DPTR,#??shadowPerof2
        MOVX	@DPTR,A
//  172 
//  173   /* set RF interrupts one notch above lowest priority (four levels available) */
//  174   IP0 |=  IP_RFERR_RF_DMA_BV;
        ORL	0xa9,#0x1
//  175   IP1 &= ~IP_RFERR_RF_DMA_BV;
        ANL	0xb9,#0xfe
//  176 
//  177   /*-------------------------------------------------------------------------------
//  178    *  Initialize MAC timer.
//  179    */
//  180 
//  181   /* set timer rollover */
//  182   T2CAPLPL = MAC_RADIO_TIMER_TICKS_PER_BACKOFF() & 0xFF;
        MOV	0xa4,#0x0
//  183   T2CAPHPH = MAC_RADIO_TIMER_TICKS_PER_BACKOFF() >> 8;
        MOV	0xa5,#0x28
//  184 
//  185   /* start timer */
//  186   T2CNF |= RUN;
        ORL	0xc3,#0x1
//  187 
//  188   /* enable timer interrupts */
//  189   T2IE = 1;
        SETB	0xb8.2
//  190 
//  191   /* configure clock to use XOSC */
//  192   SLEEP &= ~OSC_PD;                       /* turn on 16MHz RC and 32MHz XOSC */
        ANL	0xbe,#0xfb
//  193   while (!(SLEEP & XOSC_STB));            /* wait for 32MHz XOSC stable */
??macMcuInit_2:
        MOV	A,0xbe
        MOV	C,0xE0 /* A   */.6
        JNC	??macMcuInit_2
//  194   asm("NOP");                             /* chip bug workaround */
        NOP
//  195   for (i=0; i<504; i++) asm("NOP");       /* Require 63us delay for Rev B */
        MOV	R0,#-0x8
        MOV	R1,#0x1
??macMcuInit_3:
        NOP
        MOV	A,R0
        ADD	A,#-0x1
        DEC	R0
        MOV	A,R1
        ADDC	A,#-0x1
        MOV	R1,A
        MOV	A,R0
        JNZ	??macMcuInit_4
        MOV	A,R1
??macMcuInit_4:
        JNZ	??macMcuInit_3
//  196   CLKCON = (0x00 | OSC_32KHZ);            /* 32MHz XOSC */
        MOV	0xc6,#0x0
//  197   while (CLKCON != (0x00 | OSC_32KHZ));
??macMcuInit_5:
        MOV	A,0xc6
        JNZ	??macMcuInit_5
//  198   SLEEP |= OSC_PD;                        /* turn off 16MHz RC */
        ORL	0xbe,#0x4
//  199   
//  200   
//  201  /*----------------------------------------------------------------------------------------------
//  202   *  Initialize random seed value.
//  203   */
//  204 
//  205   /* turn on radio power */
//  206   RFPWR &= ~RREG_RADIO_PD;
        MOV	DPTR,#-0x20e9
        MOVX	A,@DPTR
        CLR	0xE0 /* A   */.3
        MOVX	@DPTR,A
//  207   while((RFPWR & ADI_RADIO_PD));
??macMcuInit_6:
        MOVX	A,@DPTR
        MOV	C,0xE0 /* A   */.4
        JC	??macMcuInit_6
//  208  
//  209   /*
//  210    *  Set radio for infinite reception.  Once radio reaches this state,
//  211    *  it will stay in receive mode regardless RF activity.
//  212    */
//  213   MDMCTRL1L = MDMCTRL1L_RESET_VALUE | RX_MODE_INFINITE_RECEPTION;
        MOV	A,#0x2
        MOV	DPTR,#-0x20fb
        MOVX	@DPTR,A
//  214   
//  215   /* turn on the receiver */
//  216   macRxOn();
        ; Setup parameters for call to function macRxOn
        MOV	DPTR,#(macRxOn & 0xffff)
        MOV	A,#((macRxOn >> 16) & 0xff)
        LCALL	?BCALL               ; Banked call to: DPTR()
        SJMP	??macMcuInit_7
//  217 
//  218   /*
//  219    *  Wait for radio to reach infinite reception state.  Once it does,
//  220    *  The least significant bit of ADTSTH should be pretty random.
//  221    */
//  222   while (FSMSTATE != FSM_FFCTRL_STATE_RX_INF)
//  223 
//  224   /* put 16 random bits into the seed value */
//  225   {
//  226     uint16 rndSeed;
//  227     uint8  i;
//  228     
//  229     rndSeed = 0;
??macMcuInit_8:
        MOV	R0,#0x0
        MOV	R1,#0x0
//  230     
//  231     for(i=0; i<16; i++)
        MOV	R4,#0x10
//  232     {
//  233       /* use most random bit of analog to digital receive conversion to populate the random seed */
//  234       rndSeed = (rndSeed << 1) | (ADCTSTH & 0x01);
??macMcuInit_9:
        MOV	A,R0
        CLR	C
        RLC	A
        MOV	R0,A
        MOV	A,R1
        RLC	A
        MOV	R1,A
        MOV	DPTR,#-0x20c6
        MOVX	A,@DPTR
        MOV	C,0xE0 /* A   */.0
        CLR	A
        MOV	0xE0 /* A   */.0,C
        ORL	A,R0
        MOV	R0,A
//  235     }
        DEC	R4
        MOV	A,R4
        JNZ	??macMcuInit_9
//  236 
//  237     /*
//  238      *  The seed value must not be zero.  If it is, the psuedo random sequence will be always be zero.
//  239      *  There is an extremely small chance this seed could randomly be zero (more likely some type of
//  240      *  hardware problem would cause this).  The following check makes sure this does not happen.
//  241      */
//  242     if (rndSeed == 0x0000)
        MOV	A,R0
        JNZ	??macMcuInit_10
        MOV	A,R1
??macMcuInit_10:
        JNZ	??macMcuInit_11
//  243     {
//  244       rndSeed = 0xBEEF; /* completely arbitrary "random" value */
        MOV	R0,#-0x11
        MOV	R1,#-0x42
//  245     }
//  246 
//  247     /*
//  248      *  Two writes to RNDL will set the random seed.  A write to RNDL copies current contents
//  249      *  of RNDL to RNDH before writing new the value to RNDL.
//  250      */
//  251     RNDL = rndSeed & 0xFF;
??macMcuInit_11:
        MOV	A,R0
        MOV	0xbc,A
//  252     RNDL = rndSeed >> 8;
        MOV	A,R1
        MOV	0xbc,A