main.c

这是几个TMS320F2812应用程序举例

			break;
		case SW5_CODE :
			lcd_puts("S5");
			txd0.l=0x55555555;
			txd1.l=0x22223333;
			can_send(5);
			break;
		case SW6_CODE :
			lcd_puts("S6");
			txd0.l=0x66666666;
			txd1.l=0x12345678;
			can_send(6);
			break;
		case SW7_CODE :
			lcd_puts("S7");
			txd0.l=0x77777777;
			txd1.l=0x12345678;
			can_send(7);
			break;
		case SW8_CODE :
			lcd_puts("S8");
			txd0.l=0x88888888;
			txd1.l=0x12345678;
			can_send(8);
			break;
		default:
			lcd_puts("??");
			break;
	}
	key_code &= ~KEY_PRESSED; 	/* Clear key flag */
}  

void	cont_key_process(){
	cont_key_cnt++;
}

void init_adc(void){
// ADC init
	AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;	// Power up bandgap/reference circuitry
	delay_ms(5);                    		// Delay before powering up rest of ADC
	AdcRegs.ADCTRL3.bit.ADCPWDN = 1;		// Power up rest of ADC
	delay_us(20);                   		// Delay after powering up ADC

    AdcRegs.ADCTRL1.bit.ACQ_PS = 2;  		// Acquition window size = 3 clock
    AdcRegs.ADCTRL1.bit.CPS = 1;  			// Tclk = CLK/2
    AdcRegs.ADCTRL3.bit.ADCCLKPS = 4;  		// ADC core clock divider, HSPCLK(75MHz)/(2*4) = 9.3728MHz

	AdcRegs.ADCMAXCONV.all = 0x000f;		// 16 ch.
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;  		// Cascaded mode,SEQ1 and SEQ2 = single 16-state
    AdcRegs.ADCTRL1.bit.CONT_RUN = 1;  		// Cont. conv. mode
	
	AdcRegs.ADCCHSELSEQ1.all = 0x3210;
	AdcRegs.ADCCHSELSEQ2.all = 0x7654;
	AdcRegs.ADCCHSELSEQ3.all = 0xBA98;
	AdcRegs.ADCCHSELSEQ4.all = 0xFEDC;

}

void init_dac(void){
// SPI init for DAC (DAC7612)
	SpiaRegs.SPICCR.bit.SPISWRESET=0;	// SPI SW RESET = 0
	SpiaRegs.SPICTL.all = 0x06;			// Master mode,without delay
	SpiaRegs.SPIBRR = 7;				// 0~2=LSPCLK(37.5MHz)/4=9.375Mbps, 3~127=LSPCLK/(SPIBRR+1)
										// 7: 37.5MHz/8= 4.6875MHz
	SpiaRegs.SPICCR.all = 0x4d;			// CLOCK_POLARITY(1)=falling, 14bit length
	SpiaRegs.SPICCR.bit.SPISWRESET=1;	// SPI SW RESET = 1
	HI_LOAD;							// /LOAD = 1;
}

Uint16	t1_prd=0xfff,t1_cmp=0x800;
Uint16	t2_prd=4096,t2_cmp=1;

void	init_ev(void){
// EVA Configure T1PWM, T2PWM, PWM1-PWM6 
// Step 1  Initalize the timers
	// Initalize EVA Timer1 
	EvaRegs.T1PR = t1_prd;       // Timer1 period
	EvaRegs.T1CMPR = t1_cmp;     // Timer1 compare
	EvaRegs.T1CNT = 0x0000;      // Timer1 counter
    // TMODE = continuous up/down
	// Timer enable
	// Timer compare enable
	EvaRegs.T1CON.all = 0x0842;   

// Step 2  Setup T1PWM and T2PWM
	// Drive T1/T2 PWM by compare logic
	EvaRegs.GPTCONA.bit.TCMPOE = 1;
	// Polarity of GP Timer 1 Compare = Active low
	EvaRegs.GPTCONA.bit.T1PIN = 1;
	// Polarity of GP Timer 2 Compare = Active high
	EvaRegs.GPTCONA.bit.T2PIN = 2;

// Step 3 Enable compare for PWM1-PWM6
	EvaRegs.CMPR1 = 0x001;
	EvaRegs.CMPR2 = 0x800;
	EvaRegs.CMPR3 = 0xff0;
    
    // Compare action control.  Action that takes place
    // on a cmpare event
    // output pin 1 CMPR1 - active high
    // output pin 2 CMPR1 - active low
    // output pin 3 CMPR2 - active high
    // output pin 4 CMPR2 - active low
    // output pin 5 CMPR3 - active high
    // output pin 6 CMPR3 - active low
    EvaRegs.ACTRA.all = 0x0999;		// change 0x0666 => 0x0999
	EvaRegs.DBTCONA.all = 0x09ec; 	// Deadband: enable
    EvaRegs.COMCONA.all = 0xA600;

	// Initalize EVA Timer2 for Encoder
	EvaRegs.T2PR = 0xffff;		// Timer2 period
	EvaRegs.T2CNT = 0x0000;		// Timer2 counter
	EvaRegs.T2CON.all = 0xd870;	// FREE=SOFT=1, Dir_UP_DN,x/1,QEP
}

/* --------------------------------------------------- */
/* ISR for PIE INT9.5  (MBX0): Receive                 */
/* Connected to eCAN0-INTA  eCAN                       */
/* ----------------------------------------------------*/
ltype	rd0,rd1;
interrupt void eCAN0INT_ISR(void){  // eCAN

	int0count++;
	
	lcd_gotoxy(0,1);
	rd0.l = ECanaMboxes.MBOX0.MDL.all;
	rd1.l = ECanaMboxes.MBOX0.MDH.all;		 
	lcd_hex8(rd0.l);
	lcd_hex8(rd1.l);

	ECanaShadow.CANRMP.all = 0;				// See Note 1
	ECanaShadow.CANRMP.bit.RMP0 = 1;		// Clear RMP0
	ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;

	PieCtrlRegs.PIEACK.bit.ACK9 = 1;    // Enables PIE to drive a pulse into the CPU
}

/* --------------------------------------------------- */
/* ISR for PIE INT9.6 (MBX1): Transmit                 */
/* Connected to eCAN1-INTA  eCAN                       */
/* ----------------------------------------------------*/
interrupt void eCAN1INT_ISR(void){  // eCAN

	int1count++;

	ECanaShadow.CANTA.all = 0;
	ECanaShadow.CANTA.bit.TA1 = 1;
	ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;

	PieCtrlRegs.PIEACK.bit.ACK9 = 1;    // Enables PIE to drive a pulse into the CPU
}

void init_can(void){
    // eCAN control registers require 32-bit access. 
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access.  One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access. 
     
    // Read the entire register into a shadow register.  This access
    // will be 32-bits.  Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write. 

/* Initialize the CAN module */
	InitECan();

    ECanaMboxes.MBOX1.MSGID.all = 0x80000000; // IDE=1,
    ECanaMboxes.MBOX0.MSGID.all = 0xc0000000; // IDE=1,AME=1

	ECanaRegs.CANMD.bit.MD0 = 1;		// MBX0 = Receive
	ECanaRegs.CANMD.bit.MD1 = 0;		// MBX1 = Transmit
	
	ECanaRegs.CANME.bit.ME0 = 1;		// MBX0 enable

	ECanaLAMRegs.LAM0.all = 0xffffffff;	// LAMI=1, don't care
	
	PieCtrlRegs.PIEIER9.bit.INTx5 = 1;  // Enable INTx.5 of INT9 (eCAN0INT)
	PieCtrlRegs.PIEIER9.bit.INTx6 = 1;  // Enable INTx.6 of INT9 (eCAN1INT)

    ECanaRegs.CANGIM.bit.I0EN = 1;     	// Enable eCAN0INT 
    ECanaRegs.CANGIM.bit.I1EN = 1;     	// Enable eCAN1INT 

	ECanaRegs.CANMIM.bit.MIM0 = 1;		// Mailbox Interrupt Mask Register, MBX0 Interrupt enable
	ECanaRegs.CANMIM.bit.MIM1 = 1;		// Mailbox Interrupt Mask Register, MBX1 Interrupt enable	

    ECanaRegs.CANGIM.bit.GIL = 0;	   	// GIL value determines eCAN(0/1)INT
	
	ECanaRegs.CANMIL.bit.MIL0 = 0;		// Mailbox Interrupt Level Register, MBX0 Interrupt 0
	ECanaRegs.CANMIL.bit.MIL1 = 1;		// Mailbox Interrupt Level Register, MBX1 Interrupt 1	
	
	PieVectTable.ECAN0INTA = &eCAN0INT_ISR;
	PieVectTable.ECAN1INTA = &eCAN1INT_ISR;	

	IER |= M_INT9;

	EDIS;
}

void main(void){

// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
	InitSysCtrl();

// Init.GPIO
	init_gpio();	

// Disable and clear all CPU interrupts:
	DINT;
	IER = 0x0000;
	IFR = 0x0000;

// Initialize Pie Control Registers To Default State:
	InitPieCtrl();

// Initialize the PIE Vector Table To a Known State:
// This function populates the PIE vector table with pointers
// to the shell ISR functions found in DSP28_DefaultIsr.c.
	InitPieVectTable();	
	
	EALLOW;	// This is needed to write to EALLOW protected registers

	PieVectTable.TINT0 = &cpu_timer0_isr;	// for TINT0
	PieVectTable.XINT1 = &xint1_isr;		// for XINT1
	PieVectTable.XINT2 = &xint2_isr;		// for XINT2
	
	EDIS;       // This is needed to disable write to EALLOW protected registers

    InitCpuTimers();
//	ConfigCpuTimer(&CpuTimer0, 100, 1000000);	// 100MHz CPU Freq, 1 second Period (in uSeconds)
//	ConfigCpuTimer(&CpuTimer0, 150, 500000);	// 150MHz CPU Freq, 0.5 sec Period (in uSeconds)
//	ConfigCpuTimer(&CpuTimer0, 150, 10);		// 150MHz CPU Freq, 10 usec Period (in uSeconds)
	ConfigCpuTimer(&CpuTimer0, 150, 1000);		// 150MHz CPU Freq, 1 msec Period (in uSeconds)
 	StartCpuTimer0();

// Interrupt Enable Register
	IER |= M_INT1;	// for TINT0, XINT1, XINT2
	
//	PIE : Peripheral Interrupts setting
	PieCtrlRegs.PIEIER1.bit.INTx7 = 1;		// for TINT0
	PieCtrlRegs.PIEIER1.bit.INTx4 = 1;		// for XINT1
	PieCtrlRegs.PIEIER1.bit.INTx5 = 1;		// for XINT2

	XIntruptRegs.XINT1CR.bit.POLARITY = 0;	// 0=falling,1=rising
//	XIntruptRegs.XINT1CR.bit.POLARITY = 1;	// 0=falling,1=rising
	XIntruptRegs.XINT1CR.bit.ENABLE = 1;	// 1=enable

	XIntruptRegs.XINT2CR.bit.POLARITY = 0;	// 0=falling,1=rising
//	XIntruptRegs.XINT2CR.bit.POLARITY = 1;	// 0=falling,1=rising
	XIntruptRegs.XINT2CR.bit.ENABLE = 1;	// 1=enable
	
	
// for SCI debug
	sci_debug_init();
	
// for XINTF: External Interface
	InitXintf();

// for LCD
	init_lcd();

// for ADC
	init_adc();

// for DAC(SPI)
	init_dac();

// for PWM(EV)
	init_ev();

// for SCI-B
	sci_init();

// for CAN
	init_can();

// Enable global Interrupts and higher priority real-time debug events:
	EINT;	// Enable Global interrupt INTM
	ERTM;	// Enable Global realtime interrupt DBGM

	lcd_gotoxy(0,0);
	lcd_puts("CAN:1Mbps,ext,  ");

	AD_START;

	while(1){    
		mcnt++;

		ad0 = AdcRegs.ADCRESULT0>>4;
		EvaRegs.CMPR1 = ad0;

		if(key_code & KEY_PRESSED) key_process();
		if(key_code & KEY_CONT) cont_key_process();

		delay_ms(100);
    }
}