📄 dsp281x_init.c
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//struct CPUTIMER_VARS CpuTimer2;
//---------------------------------------------------------------------------
// InitCpuTimers:
//---------------------------------------------------------------------------
// This function initializes all three CPU timers to a known state.
//
void InitCpuTimers(void)
{
// CPU Timer 0
// Initialize address pointers to respective timer registers:
CpuTimer0.RegsAddr = &CpuTimer0Regs;
// Initialize timer period to maximum:
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
CpuTimer0Regs.TPR.all = 0;
CpuTimer0Regs.TPRH.all = 0;
// Make sure timer is stopped:
CpuTimer0Regs.TCR.bit.TSS = 1;
// Reload all counter register with period value:
CpuTimer0Regs.TCR.bit.TRB = 1;
// Reset interrupt counters:
CpuTimer0.InterruptCount = 0;
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
// Do not use these two timers if you ever plan on integrating
// DSP-BIOS or another realtime OS.
//
// For this reason, the code to manipulate these two timers is
// commented out and not used in these examples.
// Initialize address pointers to respective timer registers:
// CpuTimer1.RegsAddr = &CpuTimer1Regs;
// CpuTimer2.RegsAddr = &CpuTimer2Regs;
// Initialize timer period to maximum:
// CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
// CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
// Make sure timers are stopped:
// CpuTimer1Regs.TCR.bit.TSS = 1;
// CpuTimer2Regs.TCR.bit.TSS = 1;
// Reload all counter register with period value:
// CpuTimer1Regs.TCR.bit.TRB = 1;
// CpuTimer2Regs.TCR.bit.TRB = 1;
// Reset interrupt counters:
// CpuTimer1.InterruptCount = 0;
// CpuTimer2.InterruptCount = 0;
}
///---------------------------------------------------------------------------
// ConfigCpuTimer:
//---------------------------------------------------------------------------
// This function initializes the selected timer to the period specified
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
// and the period in "uSeconds". The timer is held in the stopped state
// after configuration.
//
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
Uint32 temp;
// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;
// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 1;
Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
// Reset interrupt counter:
Timer->InterruptCount = 0;
}
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void)
{
#if F2812
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F2812 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
// Zone 1------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING1.bit.XWRLEAD = 3;
XintfRegs.XTIMING1.bit.XWRACTIVE = 7;
XintfRegs.XTIMING1.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING1.bit.XRDLEAD = 3;
XintfRegs.XTIMING1.bit.XRDACTIVE = 7;
XintfRegs.XTIMING1.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING1.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING1.bit.USEREADY = 1;
XintfRegs.XTIMING1.bit.READYMODE = 1; // sample asynchronous
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING1.bit.XSIZE = 3;
// Zone 2------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING2.bit.XWRLEAD = 3;
XintfRegs.XTIMING2.bit.XWRACTIVE = 7;
XintfRegs.XTIMING2.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING2.bit.XRDLEAD = 3;
XintfRegs.XTIMING2.bit.XRDACTIVE = 7;
XintfRegs.XTIMING2.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING2.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING2.bit.USEREADY = 1;
XintfRegs.XTIMING2.bit.READYMODE = 1; // sample asynchronous
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING2.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;
XintfRegs.XTIMING6.bit.XWRACTIVE = 1;
XintfRegs.XTIMING6.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 1;
XintfRegs.XTIMING6.bit.XRDACTIVE = 2;
XintfRegs.XTIMING6.bit.XRDTRAIL = 0;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
XintfRegs.XTIMING7.bit.XWRACTIVE = 1;
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
XintfRegs.XTIMING7.bit.XRDACTIVE = 2;
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 0;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 0; // sample asynchronous
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
#endif
}
//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void){
EALLOW;
/* Configure eCAN pins using GPIO regs*/
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaRegs.CANMC.bit.SCB = 1;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
/* Clear all TAn bits */
ECanaRegs.CANTA.all = 0xFFFFFFFF;
/* Clear all RMPn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF;
/* Clear all interrupt flag bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters */
ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaRegs.CANBTC.bit.BRPREG = 9;
ECanaRegs.CANBTC.bit.TSEG2REG = 2;
ECanaRegs.CANBTC.bit.TSEG1REG = 10;
ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
}
/***************************************************/
/* Bit configuration parameters for 150 MHz SYSCLKOUT*/
/***************************************************/
/*
The table below shows how BRP field must be changed to achieve different bit
rates with a BT of 15, for a 80% SP:
---------------------------------------------------
BT = 15, TSEG1 = 10, TSEG2 = 2, Sampling Point = 80%
---------------------------------------------------
1 Mbps : BRP+1 = 10 : CAN clock = 15 MHz
500 kbps : BRP+1 = 20 : CAN clock = 7.5 MHz
250 kbps : BRP+1 = 40 : CAN clock = 3.75 MHz
125 kbps : BRP+1 = 80 : CAN clock = 1.875 MHz
100 kbps : BRP+1 = 100 : CAN clock = 1.5 MHz
50 kbps : BRP+1 = 200 : CAN clock = 0.75 MHz
The table below shows how to achieve different sampling points with a BT of 25:
-------------------------------------------------------------
Achieving desired SP by changing TSEG1 & TSEG2 with BT = 25
-------------------------------------------------------------
TSEG1 = 18, TSEG2 = 4, SP = 80%
TSEG1 = 17, TSEG2 = 5, SP = 76%
TSEG1 = 16, TSEG2 = 6, SP = 72%
TSEG1 = 15, TSEG2 = 7, SP = 68%
TSEG1 = 14, TSEG2 = 8, SP = 64%
The table below shows how BRP field must be changed to achieve different bit
rates with a BT of 25, for the sampling points shown above:
1 Mbps : BRP+1 = 6
500 kbps : BRP+1 = 12
250 kbps : BRP+1 = 24
125 kbps : BRP+1 = 48
100 kbps : BRP+1 = 60
50 kbps : BRP+1 = 120
*/
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