📄 dfre2.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DFRE2 IS
PORT(iclk : IN STD_LOGIC;
oclk : OUT STD_LOGIC);
END DFRE2;
ARCHITECTURE run OF DFRE2 IS
BEGIN
PROCESS (iclk)
VARIABLE fre: STD_LOGIC_VECTOR(25 DOWNTO 0);
VARIABLE OC : STD_LOGIC;
BEGIN
IF iclk'EVENT AND iclk = '1'
THEN IF fre = "01011111010111100001000000"
THEN fre := "00000000000000000000000000";
OC := NOT OC;
ELSE fre := fre + '1';
END IF;
END IF;
oclk <= OC;
END PROCESS;
END run;
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