shubio.h

xen虚拟机源代码安装包

		u64 i_rd_to:1;
		u64 i_spur_wr:1;
		u64 i_spur_rd:1;
		u64 i_rsvd:11;
		u64 i_mult_err:1;
	} ii_iprbe_fld_s;
} ii_iprbf_u_t;

/************************************************************************
 *									*
 *  This register specifies the timeout value to use for monitoring     *
 * Crosstalk credits which are used outbound to Crosstalk. An           *
 * internal counter called the Crosstalk Credit Timeout Counter         *
 * increments every 128 II clocks. The counter starts counting          *
 * anytime the credit count drops below a threshold, and resets to      *
 * zero (stops counting) anytime the credit count is at or above the    *
 * threshold. The threshold is 1 credit in direct connect mode and 2    *
 * in Crossbow connect mode. When the internal Crosstalk Credit         *
 * Timeout Counter reaches the value programmed in this register, a     *
 * Crosstalk Credit Timeout has occurred. The internal counter is not   *
 * readable from software, and stops counting at its maximum value,     *
 * so it cannot cause more than one interrupt.                          *
 *									*
 ************************************************************************/

typedef union ii_ixcc_u {
	u64 ii_ixcc_regval;
	struct {
		u64 i_time_out:26;
		u64 i_rsvd:38;
	} ii_ixcc_fld_s;
} ii_ixcc_u_t;

/************************************************************************
 *									*
 * Description:  This register qualifies all the PIO and DMA            *
 * operations launched from widget 0 towards the SHub. In               *
 * addition, it also qualifies accesses by the BTE streams.             *
 * The bits in each field of this register are cleared by the SHub      *
 * upon detection of an error which requires widget 0 or the BTE        *
 * streams to be terminated. Whether or not widget x has access         *
 * rights to this SHub is determined by an AND of the device            *
 * enable bit in the appropriate field of this register and bit 0 in    *
 * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
 * them. Incoming replies from Crosstalk are not subject to this        *
 * access control mechanism.                                            *
 *									*
 ************************************************************************/

typedef union ii_imem_u {
	u64 ii_imem_regval;
	struct {
		u64 i_w0_esd:1;
		u64 i_rsvd_3:3;
		u64 i_b0_esd:1;
		u64 i_rsvd_2:3;
		u64 i_b1_esd:1;
		u64 i_rsvd_1:3;
		u64 i_clr_precise:1;
		u64 i_rsvd:51;
	} ii_imem_fld_s;
} ii_imem_u_t;

/************************************************************************
 *									*
 * Description:  This register specifies the timeout value to use for   *
 * monitoring Crosstalk tail flits coming into the Shub in the          *
 * TAIL_TO field. An internal counter associated with this register     *
 * is incremented every 128 II internal clocks (7 bits). The counter    *
 * starts counting anytime a header micropacket is received and stops   *
 * counting (and resets to zero) any time a micropacket with a Tail     *
 * bit is received. Once the counter reaches the threshold value        *
 * programmed in this register, it generates an interrupt to the        *
 * processor that is programmed into the IIDSR. The counter saturates   *
 * (does not roll over) at its maximum value, so it cannot cause        *
 * another interrupt until after it is cleared.                         *
 * The register also contains the Read Response Timeout values. The     *
 * Prescalar is 23 bits, and counts II clocks. An internal counter      *
 * increments on every II clock and when it reaches the value in the    *
 * Prescalar field, all IPRTE registers with their valid bits set       *
 * have their Read Response timers bumped. Whenever any of them match   *
 * the value in the RRSP_TO field, a Read Response Timeout has          *
 * occurred, and error handling occurs as described in the Error        *
 * Handling section of this document.                                   *
 *									*
 ************************************************************************/

typedef union ii_ixtt_u {
	u64 ii_ixtt_regval;
	struct {
		u64 i_tail_to:26;
		u64 i_rsvd_1:6;
		u64 i_rrsp_ps:23;
		u64 i_rrsp_to:5;
		u64 i_rsvd:4;
	} ii_ixtt_fld_s;
} ii_ixtt_u_t;

/************************************************************************
 *									*
 *  Writing a 1 to the fields of this register clears the appropriate   *
 * error bits in other areas of SHub. Note that when the                *
 * E_PRB_x bits are used to clear error bits in PRB registers,          *
 * SPUR_RD and SPUR_WR may persist, because they require additional     *
 * action to clear them. See the IPRBx and IXSS Register                *
 * specifications.                                                      *
 *									*
 ************************************************************************/

typedef union ii_ieclr_u {
	u64 ii_ieclr_regval;
	struct {
		u64 i_e_prb_0:1;
		u64 i_rsvd:7;
		u64 i_e_prb_8:1;
		u64 i_e_prb_9:1;
		u64 i_e_prb_a:1;
		u64 i_e_prb_b:1;
		u64 i_e_prb_c:1;
		u64 i_e_prb_d:1;
		u64 i_e_prb_e:1;
		u64 i_e_prb_f:1;
		u64 i_e_crazy:1;
		u64 i_e_bte_0:1;
		u64 i_e_bte_1:1;
		u64 i_reserved_1:10;
		u64 i_spur_rd_hdr:1;
		u64 i_cam_intr_to:1;
		u64 i_cam_overflow:1;
		u64 i_cam_read_miss:1;
		u64 i_ioq_rep_underflow:1;
		u64 i_ioq_req_underflow:1;
		u64 i_ioq_rep_overflow:1;
		u64 i_ioq_req_overflow:1;
		u64 i_iiq_rep_overflow:1;
		u64 i_iiq_req_overflow:1;
		u64 i_ii_xn_rep_cred_overflow:1;
		u64 i_ii_xn_req_cred_overflow:1;
		u64 i_ii_xn_invalid_cmd:1;
		u64 i_xn_ii_invalid_cmd:1;
		u64 i_reserved_2:21;
	} ii_ieclr_fld_s;
} ii_ieclr_u_t;

/************************************************************************
 *									*
 *  This register controls both BTEs. SOFT_RESET is intended for        *
 * recovery after an error. COUNT controls the total number of CRBs     *
 * that both BTEs (combined) can use, which affects total BTE           *
 * bandwidth.                                                           *
 *									*
 ************************************************************************/

typedef union ii_ibcr_u {
	u64 ii_ibcr_regval;
	struct {
		u64 i_count:4;
		u64 i_rsvd_1:4;
		u64 i_soft_reset:1;
		u64 i_rsvd:55;
	} ii_ibcr_fld_s;
} ii_ibcr_u_t;

/************************************************************************
 *									*
 *  This register contains the header of a spurious read response       *
 * received from Crosstalk. A spurious read response is defined as a    *
 * read response received by II from a widget for which (1) the SIDN    *
 * has a value between 1 and 7, inclusive (II never sends requests to   *
 * these widgets (2) there is no valid IPRTE register which             *
 * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
 * not the same as the widget recorded in the IPRTE register            *
 * referenced by the TNUM. If this condition is true, and if the        *
 * IXSS[VALID] bit is clear, then the header of the spurious read       *
 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
 * errant header is thereby captured, and no further spurious read      *
 * respones are captured until IXSS[VALID] is cleared by setting the    *
 * appropriate bit in IECLR.Everytime a spurious read response is       *
 * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
 * message's SIDN field is set. This always happens, regarless of       *
 * whether a header is captured. The programmer should check            *
 * IXSM[SIDN] to determine which widget sent the spurious response,     *
 * because there may be more than one SPUR_RD bit set in the PRB        *
 * registers. The widget indicated by IXSM[SIDN] was the first          *
 * spurious read response to be received since the last time            *
 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
 * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
 * spurious messages from other widets which were detected after the    *
 * header was captured..                                                *
 *									*
 ************************************************************************/

typedef union ii_ixsm_u {
	u64 ii_ixsm_regval;
	struct {
		u64 i_byte_en:32;
		u64 i_reserved:1;
		u64 i_tag:3;
		u64 i_alt_pactyp:4;
		u64 i_bo:1;
		u64 i_error:1;
		u64 i_vbpm:1;
		u64 i_gbr:1;
		u64 i_ds:2;
		u64 i_ct:1;
		u64 i_tnum:5;
		u64 i_pactyp:4;
		u64 i_sidn:4;
		u64 i_didn:4;
	} ii_ixsm_fld_s;
} ii_ixsm_u_t;

/************************************************************************
 *									*
 *  This register contains the sideband bits of a spurious read         *
 * response received from Crosstalk.                                    *
 *									*
 ************************************************************************/

typedef union ii_ixss_u {
	u64 ii_ixss_regval;
	struct {
		u64 i_sideband:8;
		u64 i_rsvd:55;
		u64 i_valid:1;
	} ii_ixss_fld_s;
} ii_ixss_u_t;

/************************************************************************
 *									*
 *  This register enables software to access the II LLP's test port.    *
 * Refer to the LLP 2.5 documentation for an explanation of the test    *
 * port. Software can write to this register to program the values      *
 * for the control fields (TestErrCapture, TestClear, TestFlit,         *
 * TestMask and TestSeed). Similarly, software can read from this       *
 * register to obtain the values of the test port's status outputs      *
 * (TestCBerr, TestValid and TestData).                                 *
 *									*
 ************************************************************************/

typedef union ii_ilct_u {
	u64 ii_ilct_regval;
	struct {
		u64 i_test_seed:20;
		u64 i_test_mask:8;
		u64 i_test_data:20;
		u64 i_test_valid:1;
		u64 i_test_cberr:1;
		u64 i_test_flit:3;
		u64 i_test_clear:1;
		u64 i_test_err_capture:1;
		u64 i_rsvd:9;
	} ii_ilct_fld_s;
} ii_ilct_u_t;

/************************************************************************
 *									*
 *  If the II detects an illegal incoming Duplonet packet (request or   *
 * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
 * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
 * and assigns a value to the ERR_TYPE field which indicates the        *
 * specific nature of the error. The II recognizes four different       *
 * types of errors: short request packets (ERR_TYPE==2), short reply    *
 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
 * reply packets (ERR_TYPE==5). The encodings for these types of        *
 * errors were chosen to be consistent with the same types of errors    *
 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
 * the LB unit). If the II detects an illegal incoming Duplonet         *
 * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
 * the OVERRUN bit to indicate that a subsequent error has happened,    *
 * and does nothing further.                                            *
 *									*
 ************************************************************************/

typedef union ii_iieph1_u {
	u64 ii_iieph1_regval;
	struct {
		u64 i_command:7;
		u64 i_rsvd_5:1;
		u64 i_suppl:14;
		u64 i_rsvd_4:1;
		u64 i_source:14;
		u64 i_rsvd_3:1;
		u64 i_err_type:4;
		u64 i_rsvd_2:4;
		u64 i_overrun:1;
		u64 i_rsvd_1:3;
		u64 i_valid:1;
		u64 i_rsvd:13;
	} ii_iieph1_fld_s;
} ii_iieph1_u_t;

/************************************************************************
 *									*
 *  This register holds the Address field from the header flit of an    *
 * incoming erroneous Duplonet packet, along with the tail bit which    *
 * accompanied this header flit. This register is essentially an        *
 * extension of IIEPH1. Two registers were necessary because the 64     *
 * bits available in only a single register were insufficient to        *
 * capt