xenasm.s

xen虚拟机源代码安装包

	;;
	itr.d dtr[r24]=loc6
	;;
	srlz.i
	;;
	srlz.d
	;;
ia64_new_rr7_efi_vpd_not_mapped:

	// done, switch back to virtual and return
	mov r16=loc3			// r16= original psr
	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
	mov psr.l = loc3		// restore init PSR
	;;

	mov ar.pfs = loc1
	mov rp = loc0
	;;
	mov ar.rsc=loc4			// restore RSE configuration
	srlz.d				// seralize restoration of psr.l
	br.ret.sptk.many rp
END(ia64_new_rr7_efi)

#if 0 /* Not used */
#include "minstate.h"

GLOBAL_ENTRY(ia64_prepare_handle_privop)
	.prologue
	/*
	 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
	 */
	mov r16=r0
	DO_SAVE_SWITCH_STACK
	br.call.sptk.many rp=ia64_handle_privop	// stack frame setup in ivt
.ret22:	.body
	DO_LOAD_SWITCH_STACK
	br.cond.sptk.many rp			// goes to ia64_leave_kernel
END(ia64_prepare_handle_privop)

GLOBAL_ENTRY(ia64_prepare_handle_break)
	.prologue
	/*
	 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
	 */
	mov r16=r0
	DO_SAVE_SWITCH_STACK
	br.call.sptk.many rp=ia64_handle_break	// stack frame setup in ivt
.ret23:	.body
	DO_LOAD_SWITCH_STACK
	br.cond.sptk.many rp			// goes to ia64_leave_kernel
END(ia64_prepare_handle_break)

GLOBAL_ENTRY(ia64_prepare_handle_reflection)
	.prologue
	/*
	 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
	 */
	mov r16=r0
	DO_SAVE_SWITCH_STACK
	br.call.sptk.many rp=ia64_handle_reflection // stack frame setup in ivt
.ret24:	.body
	DO_LOAD_SWITCH_STACK
	br.cond.sptk.many rp			// goes to ia64_leave_kernel
END(ia64_prepare_handle_reflection)
#endif

GLOBAL_ENTRY(__get_domain_bundle)
	EX(.failure_in_get_bundle,ld8 r8=[r32],8)
	;;
	EX(.failure_in_get_bundle,ld8 r9=[r32])
	;;
	br.ret.sptk.many rp
	;;
.failure_in_get_bundle:
	mov r8=0
	;;
	mov r9=0
	;;
	br.ret.sptk.many rp
	;;
END(__get_domain_bundle)

/* derived from linux/arch/ia64/hp/sim/boot/boot_head.S */
GLOBAL_ENTRY(pal_emulator_static)
	mov r8=-1
	mov r9=256
	;;
	cmp.gtu p7,p8=r9,r32		/* r32 <= 255? */
(p7)	br.cond.sptk.few static
	;;
	mov r9=512
	;;
	cmp.gtu p7,p8=r9,r32
(p7)	br.cond.sptk.few stacked
	;;
static:	cmp.eq p7,p8=6,r32		/* PAL_PTCE_INFO */
(p8)	br.cond.sptk.few 1f
	;;
	mov r8=0			/* status = 0 */
	movl r9=0x100000000		/* tc.base */
	movl r10=0x0000000200000003	/* count[0], count[1] */
	movl r11=0x1000000000002000	/* stride[0], stride[1] */
	br.ret.sptk.few rp
1:	cmp.eq p7,p8=14,r32		/* PAL_FREQ_RATIOS */
(p8)	br.cond.sptk.few 1f
	mov r8=0			/* status = 0 */
	movl r9 =0x900000002		/* proc_ratio (1/100) */
	movl r10=0x100000100		/* bus_ratio<<32 (1/256) */
	movl r11=0x900000002		/* itc_ratio<<32 (1/100) */
	;;
1:	cmp.eq p7,p8=19,r32		/* PAL_RSE_INFO */
(p8)	br.cond.sptk.few 1f
	mov r8=0			/* status = 0 */
	mov r9=96			/* num phys stacked */
	mov r10=0			/* hints */
	mov r11=0
	br.ret.sptk.few rp
1:	cmp.eq p7,p8=1,r32		/* PAL_CACHE_FLUSH */
(p8)	br.cond.sptk.few 1f
#if 0
	mov r9=ar.lc
	movl r8=524288		/* flush 512k million cache lines (16MB) */
	;;
	mov ar.lc=r8
	movl r8=0xe000000000000000
	;;
.loop:	fc r8
	add r8=32,r8
	br.cloop.sptk.few .loop
	sync.i
	;;
	srlz.i
	;;
	mov ar.lc=r9
	mov r8=r0
	;;
1:	cmp.eq p7,p8=15,r32		/* PAL_PERF_MON_INFO */
(p8)	br.cond.sptk.few 1f
	mov r8=0			/* status = 0 */
	movl r9 =0x08122f04		/* generic=4 width=47 retired=8 
					 * cycles=18
					 */
	mov r10=0			/* reserved */
	mov r11=0			/* reserved */
	mov r16=0xffff			/* implemented PMC */
	mov r17=0x3ffff			/* implemented PMD */
	add r18=8,r29			/* second index */
	;;
	st8 [r29]=r16,16		/* store implemented PMC */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
	st8 [r29]=r0,16			/* clear remaining bits  */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
	st8 [r29]=r17,16		/* store implemented PMD */
	st8 [r18]=r0,16			/* clear remaining bits  */
	mov r16=0xf0			/* cycles count capable PMC */
	;;
	st8 [r29]=r0,16			/* clear remaining bits  */
	st8 [r18]=r0,16			/* clear remaining bits  */
	mov r17=0xf0			/* retired bundles capable PMC */
	;;
	st8 [r29]=r16,16		/* store cycles capable */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
	st8 [r29]=r0,16			/* clear remaining bits  */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
	st8 [r29]=r17,16		/* store retired bundle capable */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
	st8 [r29]=r0,16			/* clear remaining bits  */
	st8 [r18]=r0,16			/* clear remaining bits  */
	;;
1:	br.cond.sptk.few rp
#else
1:
#endif
stacked:
	br.ret.sptk.few rp
END(pal_emulator_static)

// void ia64_copy_rbs(unsigned long* dst_bspstore, unsigned long* dst_rbs_size,
//                    unsigned long* dst_rnat_p,
//                    unsigned long* src_bsp, unsigned long src_rbs_size,
//                    unsigned long src_rnat);
// Caller must mask interrupions.
// Caller must ensure that src_rbs_size isn't larger than the number
// of physical stacked registers. otherwise loadrs fault with Illegal
// Operation fault resulting in panic.
//
// r14 = r32 = dst_bspstore
// r15 = r33 = dst_rbs_size_p	
// r16 = r34 = dst_rnat_p
// r17 = r35 = src_bsp
// r18 = r36 = src_rbs_size
// r19 = r37 = src_rnat	
//
// r20 = saved ar.rsc
// r21 = saved ar.bspstore
//	
// r22 = saved_ar_rnat
// r23 = saved_ar_rp
// r24 = saved_ar_pfs	
//
// we save the value in this register and store it into [dst_rbs_size_p] and
// [dst_rnat_p] after rse opeation is done.
// r30 = return value of __ia64_copy_rbs to ia64_copy_to_rbs = dst_rbs_size
// r31 = return value of __ia64_copy_rbs to ia64_copy_to_rbs = dst_rnat
//
#define dst_bspstore		r14
#define dst_rbs_size_p		r15
#define dst_rnat_p		r16
#define src_bsp			r17
#define src_rbs_size		r18
#define src_rnat		r19

#define saved_ar_rsc		r20
#define saved_ar_bspstore	r21
#define saved_ar_rnat		r22
#define saved_rp		r23
#define saved_ar_pfs		r24

#define dst_rbs_size		r30
#define dst_rnat		r31
ENTRY(__ia64_copy_rbs)
	.prologue
	.fframe 0

	// Here cfm.{sof, sol, sor, rrb}=0 
	//
	// flush current register stack to backing store
{
	flushrs	// must be first isns in group
	srlz.i
}

	// switch to enforced lazy mode	
	mov saved_ar_rsc = ar.rsc
	;; 
	mov ar.rsc = 0
	;; 

	.save ar.bspstore, saved_ar_bspstore
	mov saved_ar_bspstore = ar.bspstore
	.save ar.rnat, saved_ar_rnat
	mov saved_ar_rnat = ar.rnat
	;;

	.body
	// load from src
	mov ar.bspstore = src_bsp
	;; 
	mov ar.rnat = src_rnat
	shl src_rbs_size = src_rbs_size,16
	;; 
	mov ar.rsc = src_rbs_size
	;;
{
	loadrs // must be first isns in group
	;;
}

	// flush to dst
	mov ar.bspstore = dst_bspstore
	;;
{
	flushrs	// must be first isns in group
	srlz.i
}
	;;
	mov dst_rbs_size = ar.bsp
	mov dst_rnat = ar.rnat
	;;
	sub dst_rbs_size = dst_rbs_size, dst_bspstore

	// switch back to the original backing store
	.restorereg ar.bspstore
	mov ar.bspstore = saved_ar_bspstore
	;;
	.restorereg ar.rnat
	mov ar.rnat = saved_ar_rnat
	;; 
	// restore rsc		
	mov ar.rsc = saved_ar_rsc

	;; 
	br.ret.sptk.many rp
END(__ia64_copy_rbs)

GLOBAL_ENTRY(ia64_copy_rbs)
	.prologue
	.fframe 0
	.save ar.pfs, saved_ar_pfs
	alloc saved_ar_pfs = ar.pfs, 6, 0, 0, 0
	.save.b 0x1, saved_rp
	mov saved_rp = rp

	.body
	// we play with register backing store so that we can't use
	// stacked registers.
	// save in0-in5 to static scratch registres
	mov dst_bspstore   = r32
	mov dst_rbs_size_p = r33
	mov dst_rnat_p     = r34
	mov src_bsp        = r35
	mov src_rbs_size   = r36
	mov src_rnat       = r37
	;;
	// set cfm.{sof, sol, sor, rrb}=0 to avoid nasty stacked register
	// issues related to cover by calling void __ia64_copy_rbs(void).
	// cfm.{sof, sol, sor, rrb}=0 makes things easy.
	br.call.sptk.many rp = __ia64_copy_rbs

	st8 [dst_rbs_size_p] = dst_rbs_size
	st8 [dst_rnat_p]     = dst_rnat

	.restorereg ar.pfs
	mov ar.pfs = saved_ar_pfs
	.restorereg rp
	mov rp = saved_rp
	;; 
	br.ret.sptk.many rp
END(ia64_copy_rbs)