vmx_vcpu.c

xen虚拟机源代码安装包

    new_vpsr = (old_vpsr & 0xffffffff00000000) | (value & 0xffffffff);
    VCPU(vcpu, vpsr) = new_vpsr;

    mipsr = ia64_getreg(_IA64_REG_CR_IPSR);

    /* xenoprof:
     * don't change psr.pp.
     * It is manipulated by xenoprof.
     */
    mask = 0xffffffff00000000 | IA64_PSR_IC | IA64_PSR_I 
        | IA64_PSR_DT  | IA64_PSR_PP | IA64_PSR_SI | IA64_PSR_RT;

    mipsr = (mipsr & mask) | (value & (~mask));

    if (FP_PSR(vcpu) & IA64_PSR_DFH)
         mipsr |= IA64_PSR_DFH;

    ia64_setreg(_IA64_REG_CR_IPSR, mipsr);

    switch_mm_mode_fast(vcpu, (IA64_PSR)old_vpsr, (IA64_PSR)new_vpsr);
}

#define IA64_PSR_MMU_VIRT (IA64_PSR_DT | IA64_PSR_RT | IA64_PSR_IT)
/* In fast path, psr.ic = 0, psr.i = 0, psr.bn = 0
 * so that no tlb miss is allowed.
 */
void vmx_vcpu_rfi_fast(VCPU *vcpu)
{
    /* TODO: Only allowed for current vcpu */
    u64 vifs, vipsr, vpsr, mipsr, mask;
    vipsr = VCPU(vcpu, ipsr);
    vpsr = VCPU(vcpu, vpsr);
    vifs = VCPU(vcpu, ifs);
    if (vipsr & IA64_PSR_BN) {
        if(!(vpsr & IA64_PSR_BN))
             vmx_asm_bsw1();
    } else if (vpsr & IA64_PSR_BN)
             vmx_asm_bsw0();

    /*
     *  For those IA64_PSR bits: id/da/dd/ss/ed/ia
     *  Since these bits will become 0, after success execution of each
     *  instruction, we will change set them to mIA64_PSR
     */
    VCPU(vcpu, vpsr) = vipsr & (~ (IA64_PSR_ID |IA64_PSR_DA 
                | IA64_PSR_DD | IA64_PSR_ED | IA64_PSR_IA));    

    /*
     * All vIA64_PSR bits shall go to mPSR (v->tf->tf_special.psr)
     * , except for the following bits:
     * ic/i/dt/si/rt/mc/it/bn/vm
     */
    /* xenoprof */
    mask = (IA64_PSR_IC | IA64_PSR_I | IA64_PSR_DT | IA64_PSR_SI |
            IA64_PSR_RT | IA64_PSR_MC | IA64_PSR_IT | IA64_PSR_BN |
            IA64_PSR_VM | IA64_PSR_PP);
    mipsr = ia64_getreg(_IA64_REG_CR_IPSR);
    mipsr = (mipsr & mask) | (vipsr & (~mask));

    if (FP_PSR(vcpu) & IA64_PSR_DFH)
         mipsr |= IA64_PSR_DFH;

    ia64_setreg(_IA64_REG_CR_IPSR, mipsr);
    vmx_ia64_set_dcr(vcpu);

    if(vifs >> 63)
        ia64_setreg(_IA64_REG_CR_IFS, vifs);

    ia64_setreg(_IA64_REG_CR_IIP, VCPU(vcpu, iip));

    switch_mm_mode_fast(vcpu, (IA64_PSR)vpsr, (IA64_PSR)vipsr);
}

/* In fast path, psr.ic = 0, psr.i = 0, psr.bn = 0
 * so that no tlb miss is allowed.
 */
void vmx_vcpu_ssm_fast(VCPU *vcpu, u64 imm24)
{
    u64  old_vpsr, new_vpsr, mipsr;

    old_vpsr = VCPU(vcpu, vpsr);
    new_vpsr = old_vpsr | imm24;

    VCPU(vcpu, vpsr) = new_vpsr;

    mipsr = ia64_getreg(_IA64_REG_CR_IPSR);
    /* xenoprof:
     * don't change psr.pp.
     * It is manipulated by xenoprof.
     */
    mipsr |= imm24 & (~IA64_PSR_PP);
    ia64_setreg(_IA64_REG_CR_IPSR, mipsr);

    switch_mm_mode_fast(vcpu, (IA64_PSR)old_vpsr, (IA64_PSR)new_vpsr);
}

/* In fast path, psr.ic = 0, psr.i = 0, psr.bn = 0
 * so that no tlb miss is allowed.
 */
void vmx_vcpu_rsm_fast(VCPU *vcpu, u64 imm24)
{
    u64  old_vpsr, new_vpsr, mipsr;

    old_vpsr = VCPU(vcpu, vpsr);
    new_vpsr = old_vpsr & ~imm24;

    VCPU(vcpu, vpsr) = new_vpsr;

    mipsr = ia64_getreg(_IA64_REG_CR_IPSR);
    /* xenoprof:
     * don't change psr.pp.
     * It is manipulated by xenoprof.
     */
    mipsr &= (~imm24) | IA64_PSR_PP;
    mipsr |= IA64_PSR_IC | IA64_PSR_I | IA64_PSR_DT | IA64_PSR_SI;

    if (FP_PSR(vcpu) & IA64_PSR_DFH)
         mipsr |= IA64_PSR_DFH;

    ia64_setreg(_IA64_REG_CR_IPSR, mipsr);

    switch_mm_mode_fast(vcpu, (IA64_PSR)old_vpsr, (IA64_PSR)new_vpsr);
}

IA64FAULT vmx_vcpu_rfi(VCPU *vcpu)
{
    // TODO: Only allowed for current vcpu
    u64 ifs, psr;
    REGS *regs = vcpu_regs(vcpu);
    psr = VCPU(vcpu,ipsr);
    if (psr & IA64_PSR_BN)
        vcpu_bsw1(vcpu);
    else
        vcpu_bsw0(vcpu);
    vmx_vcpu_set_psr(vcpu,psr);
    vmx_ia64_set_dcr(vcpu);
    ifs=VCPU(vcpu,ifs);
    if(ifs>>63)
        regs->cr_ifs = ifs;
    regs->cr_iip = VCPU(vcpu,iip);
    return (IA64_NO_FAULT);
}


#if 0
IA64FAULT
vmx_vcpu_get_bgr(VCPU *vcpu, unsigned int reg, u64 *val)
{
    IA64_PSR vpsr;

    vpsr.val = vmx_vcpu_get_psr(vcpu);
    if ( vpsr.bn ) {
        *val=VCPU(vcpu,vgr[reg-16]);
        // Check NAT bit
        if ( VCPU(vcpu,vnat) & (1UL<<(reg-16)) ) {
            // TODO
            //panic ("NAT consumption fault\n");
            return IA64_FAULT;
        }

    }
    else {
        *val=VCPU(vcpu,vbgr[reg-16]);
        if ( VCPU(vcpu,vbnat) & (1UL<<reg) ) {
            //panic ("NAT consumption fault\n");
            return IA64_FAULT;
        }

    }
    return IA64_NO_FAULT;
}

IA64FAULT
vmx_vcpu_set_bgr(VCPU *vcpu, unsigned int reg, u64 val,int nat)
{
    IA64_PSR vpsr;
    vpsr.val = vmx_vcpu_get_psr(vcpu);
    if ( vpsr.bn ) {
        VCPU(vcpu,vgr[reg-16]) = val;
        if(nat){
            VCPU(vcpu,vnat) |= ( 1UL<<(reg-16) );
        }else{
            VCPU(vcpu,vbnat) &= ~( 1UL<<(reg-16) );
        }
    }
    else {
        VCPU(vcpu,vbgr[reg-16]) = val;
        if(nat){
            VCPU(vcpu,vnat) |= ( 1UL<<(reg) );
        }else{
            VCPU(vcpu,vbnat) &= ~( 1UL<<(reg) );
        }
    }
    return IA64_NO_FAULT;
}

#endif
#if 0
IA64FAULT
vmx_vcpu_get_gr(VCPU *vcpu, unsigned reg, u64 * val)
{
    REGS *regs=vcpu_regs(vcpu);
    int nat;
    //TODO, Eddie
    if (!regs) return 0;
#if 0
    if (reg >= 16 && reg < 32) {
        return vmx_vcpu_get_bgr(vcpu,reg,val);
    }
#endif
    getreg(reg,val,&nat,regs);    // FIXME: handle NATs later
    if(nat){
        return IA64_FAULT;
    }
    return IA64_NO_FAULT;
}

// returns:
//   IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
//   IA64_NO_FAULT otherwise

IA64FAULT
vmx_vcpu_set_gr(VCPU *vcpu, unsigned reg, u64 value, int nat)
{
    REGS *regs = vcpu_regs(vcpu);
    long sof = (regs->cr_ifs) & 0x7f;
    //TODO Eddie

    if (!regs) return IA64_ILLOP_FAULT;
    if (reg >= sof + 32) return IA64_ILLOP_FAULT;
#if 0
    if ( reg >= 16 && reg < 32 ) {
        return vmx_vcpu_set_bgr(vcpu,reg, value, nat);
    }
#endif
    setreg(reg,value,nat,regs);
    return IA64_NO_FAULT;
}

#endif

/*
    VPSR can't keep track of below bits of guest PSR
    This function gets guest PSR
 */

u64 vmx_vcpu_get_psr(VCPU *vcpu)
{
    u64 mask;
    REGS *regs = vcpu_regs(vcpu);
    mask = IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL |
           IA64_PSR_MFH | IA64_PSR_CPL | IA64_PSR_RI;
    return (VCPU(vcpu, vpsr) & ~mask) | (regs->cr_ipsr & mask);
}

IA64FAULT vmx_vcpu_reset_psr_sm(VCPU *vcpu, u64 imm24)
{
    u64 vpsr;
    vpsr = vmx_vcpu_get_psr(vcpu);
    vpsr &= (~imm24);
    vmx_vcpu_set_psr(vcpu, vpsr);
    return IA64_NO_FAULT;
}


IA64FAULT vmx_vcpu_set_psr_sm(VCPU *vcpu, u64 imm24)
{
    u64 vpsr;
    vpsr = vmx_vcpu_get_psr(vcpu);
    vpsr |= imm24;
    vmx_vcpu_set_psr(vcpu, vpsr);
    return IA64_NO_FAULT;
}


IA64FAULT vmx_vcpu_set_psr_l(VCPU *vcpu, u64 val)
{
    val = (val & MASK(0, 32)) | (vmx_vcpu_get_psr(vcpu) & MASK(32, 32));
    vmx_vcpu_set_psr(vcpu, val);
    return IA64_NO_FAULT;
}

IA64FAULT
vmx_vcpu_set_tpr(VCPU *vcpu, u64 val)
{
    VCPU(vcpu,tpr)=val;
    vcpu->arch.irq_new_condition = 1;
    return IA64_NO_FAULT;
}