vmx_ivt.s

xen虚拟机源代码安装包

    mov cr.ipsr=r28	// ipsr.vm=1
    mov r17=cr.isr
    mov r23=r31
//  mov r22=b0		// b0 is clobbered in vmx_nested_dtlb_miss
    adds r16=IA64_VPD_BASE_OFFSET,r21
    ;;
    ld8 r18=[r16]
    ;;
    adds r19=VPD(VPSR),r18
    ;;
    ld8 r19=[r19]
    br.sptk ia64_vmm_entry
    ;;
END(vmx_dirty_bit)

    .org vmx_ia64_ivt+0x2400
/////////////////////////////////////////////////////////////////////////////////////////
// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
ENTRY(vmx_iaccess_bit)
    VMX_DBG_FAULT(9)
    VMX_REFLECT(9)
END(vmx_iaccess_bit)

    .org vmx_ia64_ivt+0x2800
/////////////////////////////////////////////////////////////////////////////////////////
// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
ENTRY(vmx_daccess_bit)
    VMX_DBG_FAULT(10)
    VMX_REFLECT(10)
END(vmx_daccess_bit)

    .org vmx_ia64_ivt+0x2c00
/////////////////////////////////////////////////////////////////////////////////////////
// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
ENTRY(vmx_break_fault)
    VMX_DBG_FAULT(11)
    mov r31=pr
    mov r19=11
    mov r17=cr.iim
    mov r29=cr.ipsr
    ;;
    tbit.z p6,p0=r29,IA64_PSR_VM_BIT
(p6)br.sptk.many vmx_dispatch_break_fault /* make sure before access [r21] */
    adds r22=IA64_VCPU_BREAKIMM_OFFSET, r21
    ;;
    ld4 r22=[r22]
    extr.u r24=r29,IA64_PSR_CPL0_BIT,2
    cmp.ltu p6,p0=NR_hypercalls,r2
    ;;
    cmp.ne.or p6,p0=r22,r17
    cmp.ne.or p6,p0=r0,r24
(p6) br.sptk.many vmx_dispatch_break_fault
    ;;
   /*
    * The streamlined system call entry/exit paths only save/restore the initial part
    * of pt_regs.  This implies that the callers of system-calls must adhere to the
    * normal procedure calling conventions.
    *
    *   Registers to be saved & restored:
    *   CR registers: cr.ipsr, cr.iip, cr.ifs
    *   AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
    *   others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
    *   Registers to be restored only:
    *   r8-r11: output value from the system call.
    *
    * During system call exit, scratch registers (including r15) are modified/cleared
    * to prevent leaking bits from kernel to user level.
    */
   
    mov r14=r21				// save r21 before bsw.1
    bsw.1				// B (6 cyc) switch to bank 1
    ;;   
    mov r29=cr.ipsr			// M2 (12 cyc)
    mov r31=pr				// I0 (2 cyc)
    mov r16=r14
    mov r15=r2

    mov r17=cr.iim			// M2 (2 cyc)
    mov.m r27=ar.rsc			// M2 (12 cyc)

    mov.m ar.rsc=0			// M2
    mov.m r21=ar.fpsr			// M2 (12 cyc)
    mov r19=b6				// I0 (2 cyc)
    ;;
    mov.m r23=ar.bspstore		// M2 (12 cyc)
    mov.m r24=ar.rnat			// M2 (5 cyc)
    mov.i r26=ar.pfs			// I0 (2 cyc)

    invala				// M0|1
    nop.m 0				// M
    mov r20=r1				// A			save r1

    nop.m 0
    movl r30=ia64_hypercall_table	// X

    mov r28=cr.iip			// M2 (2 cyc)
   //
   // From this point on, we are definitely on the syscall-path
   // and we can use (non-banked) scratch registers.
   //
///////////////////////////////////////////////////////////////////////
    mov r1=r16				// A    move task-pointer to "addl"-addressable reg
    mov r2=r16				// A    setup r2 for ia64_syscall_setup

    mov r3=NR_hypercalls - 1
    ;;
    mov r9=r0               		// force flags = 0
    extr.u r8=r29,41,2			// I0   extract ei field from cr.ipsr

    shladd r30=r15,3,r30		// A    r30 = hcall_table + 8*syscall
    addl r22=IA64_RBS_OFFSET,r1		// A    compute base of RBS
    cmp.leu p6,p7=r15,r3		// A    syscall number in range?
    ;;

    lfetch.fault.excl.nt1 [r22]		// M0|1 prefetch RBS
(p6) ld8 r30=[r30]			// M0|1 load address of syscall entry point
    tnat.nz.or p7,p0=r15		// I0	is syscall nr a NaT?

    mov.m ar.bspstore=r22		// M2   switch to kernel RBS
    cmp.eq p8,p9=2,r8			// A    isr.ei==2?
    ;;

(p8) mov r8=0				// A    clear ei to 0
(p7) movl r30=do_ni_hypercall		// X

(p8) adds r28=16,r28			// A    switch cr.iip to next bundle
(p9) adds r8=1,r8			// A    increment ei to next slot
    nop.i 0
    ;;

    mov.m r25=ar.unat			// M2 (5 cyc)
    dep r29=r8,r29,41,2			// I0   insert new ei into cr.ipsr
   //
   // If any of the above loads miss in L1D, we'll stall here until
   // the data arrives.
   //
///////////////////////////////////////////////////////////////////////
    mov b6=r30				// I0   setup syscall handler branch reg early

    mov r18=ar.bsp				// M2 (12 cyc)
   ;;
    addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A    compute base of memory stack
    br.call.sptk.many b7=ia64_hypercall_setup	// B
1:
    mov ar.rsc=0x3				// M2   set eager mode, pl 0, LE, loadrs=0
    ;;
    ssm psr.ic | PSR_DEFAULT_BITS		// M2	now it's safe to re-enable intr.-collection
    ;;

    srlz.i					// M0   ensure interruption collection is on
(p15)   ssm psr.i				// M2   restore psr.i
    br.call.sptk.many b0=b6			// B    invoke syscall-handker (ignore return addr)
	;; 
	//restore hypercall argument if continuation
	adds r2=IA64_VCPU_HYPERCALL_CONTINUATION_OFS,r13
	;;
	ld1 r20=[r2]
	;;
	st1 [r2]=r0
	cmp.ne p6,p0=r20,r0
	;;
(p6)	adds r2=PT(R16)+16,r12
(p6)	adds r3=PT(R17)+16,r12
	;;
(p6)	ld8 r32=[r2],16
(p6)	ld8 r33=[r3],16
	;;
(p6)	ld8 r34=[r2],16
(p6)	ld8 r35=[r3],16
	;;
(p6)	ld8 r36=[r2],16
	;;
	br.sptk.many ia64_leave_hypercall
	;;

   VMX_FAULT(11)
END(vmx_break_fault)

    .org vmx_ia64_ivt+0x3000
/////////////////////////////////////////////////////////////////////////////////////////
// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
ENTRY(vmx_interrupt)
    VMX_DBG_FAULT(12)
    mov r31=pr		// prepare to save predicates
    mov r19=12
    br.sptk vmx_dispatch_interrupt
END(vmx_interrupt)

    .org vmx_ia64_ivt+0x3400
/////////////////////////////////////////////////////////////////////////////////////////
// 0x3400 Entry 13 (size 64 bundles) Reserved
ENTRY(vmx_virtual_exirq)
    VMX_DBG_FAULT(13)
    mov r31=pr
    mov r19=13
    br.sptk vmx_dispatch_vexirq
END(vmx_virtual_exirq)

    .org vmx_ia64_ivt+0x3800
/////////////////////////////////////////////////////////////////////////////////////////
// 0x3800 Entry 14 (size 64 bundles) Reserved
    VMX_DBG_FAULT(14)
    VMX_FAULT(14)
    // this code segment is from 2.6.16.13
    
    /*
     * There is no particular reason for this code to be here, other than that
     * there happens to be space here that would go unused otherwise.  If this
     * fault ever gets "unreserved", simply moved the following code to a more
     * suitable spot...
     *
     * ia64_syscall_setup() is a separate subroutine so that it can
     *	allocate stacked registers so it can safely demine any
     *	potential NaT values from the input registers.
     *
     * On entry:
     *	- executing on bank 0 or bank 1 register set (doesn't matter)
     *	-  r1: stack pointer
     *	-  r2: current task pointer
     *	-  r3: preserved
     *	- r11: original contents (saved ar.pfs to be saved)
     *	- r12: original contents (sp to be saved)
     *	- r13: original contents (tp to be saved)
     *	- r15: original contents (syscall # to be saved)
     *	- r18: saved bsp (after switching to kernel stack)
     *	- r19: saved b6
     *	- r20: saved r1 (gp)
     *	- r21: saved ar.fpsr
     *	- r22: kernel's register backing store base (krbs_base)
     *	- r23: saved ar.bspstore
     *	- r24: saved ar.rnat
     *	- r25: saved ar.unat
     *	- r26: saved ar.pfs
     *	- r27: saved ar.rsc
     *	- r28: saved cr.iip
     *	- r29: saved cr.ipsr
     *	- r31: saved pr
     *	-  b0: original contents (to be saved)
     * On exit:
     *	-  p10: TRUE if syscall is invoked with more than 8 out
     *		registers or r15's Nat is true
     *	-  r1: kernel's gp
     *	-  r3: preserved (same as on entry)
     *	-  r8: -EINVAL if p10 is true
     *	- r12: points to kernel stack
     *	- r13: points to current task
     *	- r14: preserved (same as on entry)
     *	- p13: preserved
     *	- p15: TRUE if interrupts need to be re-enabled
     *	- ar.fpsr: set to kernel settings
     *	-  b6: preserved (same as on entry)
     */
ENTRY(ia64_hypercall_setup)
#if PT(B6) != 0
# error This code assumes that b6 is the first field in pt_regs.
#endif
    st8 [r1]=r19				// save b6
    add r16=PT(CR_IPSR),r1			// initialize first base pointer
    add r17=PT(R11),r1			// initialize second base pointer
    ;;
    alloc r19=ar.pfs,8,0,0,0		// ensure in0-in7 are writable
    st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR)	// save cr.ipsr
    tnat.nz p8,p0=in0

    st8.spill [r17]=r11,PT(CR_IIP)-PT(R11)	// save r11
    tnat.nz p9,p0=in1
//(pKStk) mov r18=r0				// make sure r18 isn't NaT
    ;;

    st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS)	// save ar.pfs
    st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP)	// save cr.iip
    mov r28=b0				// save b0 (2 cyc)
    ;;

    st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT)	// save ar.unat
    dep r19=0,r19,38,26			// clear all bits but 0..37 [I0]
(p8)    mov in0=-1
    ;;

    st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS)	// store ar.pfs.pfm in cr.ifs
    extr.u r11=r19,7,7	// I0		// get sol of ar.pfs
    and r8=0x7f,r19		// A		// get sof of ar.pfs

    st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
    tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
(p9)    mov in1=-1
    ;;

//(pUStk) sub r18=r18,r22				// r18=RSE.ndirty*8
    sub r18=r18,r22				// r18=RSE.ndirty*8
    tnat.nz p10,p0=in2
    add r11=8,r11
    ;;
//(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16		// skip over ar_rnat field
//(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17	// skip over ar_bspstore field
    tnat.nz p11,p0=in3
    ;;
(p10)   mov in2=-1
    tnat.nz p12,p0=in4				// [I0]
(p11)   mov in3=-1
    ;;
//(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT)	// save ar.rnat
    st8 [r16]=r24,PT(PR)-PT(AR_RNAT)	// save ar.rnat
//(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE)	// save ar.bspstore
    st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE)	// save ar.bspstore	
    shl r18=r18,16				// compute ar.rsc to be used for "loadrs"
    ;;
    st8 [r16]=r31,PT(LOADRS)-PT(PR)		// save predicates
    st8 [r17]=r28,PT(R1)-PT(B0)		// save b0
    tnat.nz p13,p0=in5				// [I0]
    ;;
    st8 [r16]=r18,PT(R12)-PT(LOADRS)	// save ar.rsc value for "loadrs"
    st8.spill [r17]=r20,PT(R13)-PT(R1)	// save original r1
(p12)   mov in4=-1
    ;;

.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12)	// save r12
.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13)		// save r13
(p13)   mov in5=-1
    ;;
    st8 [r16]=r21,PT(R8)-PT(AR_FPSR)	// save ar.fpsr
    tnat.nz p13,p0=in6
    cmp.lt p10,p9=r11,r8	// frame size can't be more than local+8
    ;;
    mov r8=1
(p9)    tnat.nz p10,p0=r15
    adds r12=-16,r1		// switch to kernel memory stack (with 16 bytes of scratch)

    st8.spill [r17]=r15			// save r15
    tnat.nz p8,p0=in7
    nop.i 0

    mov r13=r2				// establish `current'
    movl r1=__gp				// establish kernel global pointer
    ;;
    st8 [r16]=r8		// ensure pt_regs.r8 != 0 (see handle_syscall_error)
(p13)   mov in6=-1
(p8)    mov in7=-1

    cmp.eq pSys,pNonSys=r0,r0		// set pSys=1, pNonSys=0
    movl r17=FPSR_DEFAULT
    ;;
    mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
(p10)   mov r8=-EINVAL
    br.ret.sptk.many b7
END(ia64_hypercall_setup)


    .org vmx_ia64_ivt+0x3c00
/////////////////////////////////////////////////////////////////////////////////////////
// 0x3c00 Entry 15 (size 64 bundles) Reserved
    VMX_DBG_FAULT(15)
    VMX_FAULT(15)


    .org vmx_ia64_ivt+0x4000
/////////////////////////////////////////////////////////////////////////////////////////
// 0x4000 Entry 16 (size 64 bundles) Reserved
    VMX_DBG_FAULT(16)
    VMX_FAULT(16)

    .org vmx_ia64_ivt+0x4400
/////////////////////////////////////////////////////////////////////////////////////////
// 0x4400 Entry 17 (size 64 bundles) Reserved
    VMX_DBG_FAULT(17)
    VMX_FAULT(17)

    .org vmx_ia64_ivt+0x4800
/////////////////////////////////////////////////////////////////////////////////////////
// 0x4800 Entry 18 (size 64 bundles) Reserved
    VMX_DBG_FAULT(18)
    VMX_FAULT(18)

    .org vmx_ia64_ivt+0x4c00
/////////////////////////////////////////////////////////////////////////////////////////
// 0x4c00 Entry 19 (size 64 bundles) Reserved
    VMX_DBG_FAULT(19)
    VMX_FAULT(19)

    .org vmx_ia64_ivt+0x5000
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5000 Entry 20 (size 16 bundles) Page Not Present
ENTRY(vmx_page_not_present)
    VMX_DBG_FAULT(20)
    VMX_REFLECT(20)
END(vmx_page_not_present)

    .org vmx_ia64_ivt+0x5100
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5100 Entry 21 (size 16 bundles) Key Permission vector
ENTRY(vmx_key_permission)
    VMX_DBG_FAULT(21)
    VMX_REFLECT(21)
END(vmx_key_permission)

    .org vmx_ia64_ivt+0x5200
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
ENTRY(vmx_iaccess_rights)
    VMX_DBG_FAULT(22)
    VMX_REFLECT(22)
END(vmx_iaccess_rights)

    .org vmx_ia64_ivt+0x5300
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
ENTRY(vmx_daccess_rights)
    VMX_DBG_FAULT(23)
    VMX_REFLECT(23)
END(vmx_daccess_rights)

    .org vmx_ia64_ivt+0x5400
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
ENTRY(vmx_general_exception)
    VMX_DBG_FAULT(24)
    VMX_REFLECT(24)
//    VMX_FAULT(24)
END(vmx_general_exception)

    .org vmx_ia64_ivt+0x5500
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
ENTRY(vmx_disabled_fp_reg)
    VMX_DBG_FAULT(25)
    VMX_REFLECT(25)
END(vmx_disabled_fp_reg)

    .org vmx_ia64_ivt+0x5600
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
ENTRY(vmx_nat_consumption)
    VMX_DBG_FAULT(26)
    VMX_REFLECT(26)
END(vmx_nat_consumption)

    .org vmx_ia64_ivt+0x5700
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5700 Entry 27 (size 16 bundles) Speculation (40)
ENTRY(vmx_speculation_vector)
    VMX_DBG_FAULT(27)
    VMX_REFLECT(27)
END(vmx_speculation_vector)

    .org vmx_ia64_ivt+0x5800
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5800 Entry 28 (size 16 bundles) Reserved
    VMX_DBG_FAULT(28)
    VMX_FAULT(28)

    .org vmx_ia64_ivt+0x5900
/////////////////////////////////////////////////////////////////////////////////////////
// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
ENTRY(vmx_debug_vector)