📄 microcode.c
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/* * Intel CPU Microcode Update Driver for Linux * * Copyright (C) 2000-2004 Tigran Aivazian * * This driver allows to upgrade microcode on Intel processors * belonging to IA-32 family - PentiumPro, Pentium II, * Pentium III, Xeon, Pentium 4, etc. * * Reference: Section 8.10 of Volume III, Intel Pentium 4 Manual, * Order Number 245472 or free download from: * * http://developer.intel.com/design/pentium4/manuals/245472.htm * * For more information, go to http://www.urbanmyth.org/microcode * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com> * Initial release. * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com> * Added read() support + cleanups. * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com> * Added 'device trimming' support. open(O_WRONLY) zeroes * and frees the saved copy of applied microcode. * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com> * Made to use devfs (/dev/cpu/microcode) + cleanups. * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com> * Added misc device support (now uses both devfs and misc). * Added MICROCODE_IOCFREE ioctl to clear memory. * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com> * Messages for error cases (non Intel & no suitable microcode). * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com> * Removed ->release(). Removed exclusive open and status bitmap. * Added microcode_rwsem to serialize read()/write()/ioctl(). * Removed global kernel lock usage. * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com> * Write 0 to 0x8B msr and then cpuid before reading revision, * so that it works even if there were no update done by the * BIOS. Otherwise, reading from 0x8B gives junk (which happened * to be 0 on my machine which is why it worked even when I * disabled update by the BIOS) * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix. * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and * Tigran Aivazian <tigran@veritas.com> * Intel Pentium 4 processor support and bugfixes. * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com> * Bugfix for HT (Hyper-Threading) enabled processors * whereby processor resources are shared by all logical processors * in a single CPU package. * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and * Tigran Aivazian <tigran@veritas.com>, * Serialize updates as required on HT processors due to speculative * nature of implementation. * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com> * Fix the panic when writing zero-length microcode chunk. * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>, * Jun Nakajima <jun.nakajima@intel.com> * Support for the microcode updates in the new format. * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com> * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl * because we no longer hold a copy of applied microcode * in kernel memory. * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com> * Fix sigmatch() macro to handle old CPUs with pf == 0. * Thanks to Stuart Swales for pointing out this bug. */#include <xen/config.h>#include <xen/lib.h>#include <xen/kernel.h>#include <xen/init.h>#include <xen/sched.h>#include <xen/smp.h>#include <xen/spinlock.h>#include <asm/current.h>#include <asm/msr.h>#include <asm/uaccess.h>#include <asm/processor.h>#define pr_debug(x...) ((void)0)#define DEFINE_MUTEX(_m) DEFINE_SPINLOCK(_m)#define mutex_lock(_m) spin_lock(_m)#define mutex_unlock(_m) spin_unlock(_m)#define vmalloc(_s) xmalloc_bytes(_s)#define vfree(_p) xfree(_p)#if 0MODULE_DESCRIPTION("Intel CPU (IA-32) Microcode Update Driver");MODULE_AUTHOR("Tigran Aivazian <tigran@veritas.com>");MODULE_LICENSE("GPL");#endifstatic int verbose;boolean_param("microcode.verbose", verbose);#define MICROCODE_VERSION "1.14a"#define DEFAULT_UCODE_DATASIZE (2000) /* 2000 bytes */#define MC_HEADER_SIZE (sizeof (microcode_header_t)) /* 48 bytes */#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) /* 2048 bytes */#define EXT_HEADER_SIZE (sizeof (struct extended_sigtable)) /* 20 bytes */#define EXT_SIGNATURE_SIZE (sizeof (struct extended_signature)) /* 12 bytes */#define DWSIZE (sizeof (u32))#define get_totalsize(mc) \ (((microcode_t *)mc)->hdr.totalsize ? \ ((microcode_t *)mc)->hdr.totalsize : DEFAULT_UCODE_TOTALSIZE)#define get_datasize(mc) \ (((microcode_t *)mc)->hdr.datasize ? \ ((microcode_t *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)#define sigmatch(s1, s2, p1, p2) \ (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)/* serialize access to the physical write to MSR 0x79 */static DEFINE_SPINLOCK(microcode_update_lock);/* no concurrent ->write()s are allowed on /dev/cpu/microcode */static DEFINE_MUTEX(microcode_mutex);static void __user *user_buffer; /* user area microcode data buffer */static unsigned int user_buffer_size; /* it's size */typedef enum mc_error_code { MC_SUCCESS = 0, MC_IGNORED = 1, MC_NOTFOUND = 2, MC_MARKED = 3, MC_ALLOCATED = 4,} mc_error_code_t;static struct ucode_cpu_info { unsigned int sig; unsigned int pf, orig_pf; unsigned int rev; unsigned int cksum; mc_error_code_t err; microcode_t *mc;} ucode_cpu_info[NR_CPUS]; static void collect_cpu_info (void *unused){ int cpu_num = smp_processor_id(); struct cpuinfo_x86 *c = cpu_data + cpu_num; struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; unsigned int val[2]; uci->sig = uci->pf = uci->rev = uci->cksum = 0; uci->err = MC_NOTFOUND; uci->mc = NULL; if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || cpu_has(c, X86_FEATURE_IA64)) { printk(KERN_ERR "microcode: CPU%d not a capable Intel processor\n", cpu_num); return; } else { uci->sig = cpuid_eax(0x00000001); if ((c->x86_model >= 5) || (c->x86 > 6)) { /* get processor flags from MSR 0x17 */ rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); uci->pf = 1 << ((val[1] >> 18) & 7); } uci->orig_pf = uci->pf; } wrmsr(MSR_IA32_UCODE_REV, 0, 0); /* see notes above for revision 1.07. Apparent chip bug */ sync_core(); /* get the current revision from MSR 0x8B */ rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev); pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n", uci->sig, uci->pf, uci->rev);}static inline void mark_microcode_update (int cpu_num, microcode_header_t *mc_header, int sig, int pf, int cksum){ struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; pr_debug("Microcode Found.\n"); pr_debug(" Header Revision 0x%x\n", mc_header->hdrver); pr_debug(" Loader Revision 0x%x\n", mc_header->ldrver); pr_debug(" Revision 0x%x \n", mc_header->rev); pr_debug(" Date %x/%x/%x\n", ((mc_header->date >> 24 ) & 0xff), ((mc_header->date >> 16 ) & 0xff), (mc_header->date & 0xFFFF)); pr_debug(" Signature 0x%x\n", sig); pr_debug(" Type 0x%x Family 0x%x Model 0x%x Stepping 0x%x\n", ((sig >> 12) & 0x3), ((sig >> 8) & 0xf), ((sig >> 4) & 0xf), ((sig & 0xf))); pr_debug(" Processor Flags 0x%x\n", pf); pr_debug(" Checksum 0x%x\n", cksum); if (mc_header->rev < uci->rev) { if (uci->err == MC_NOTFOUND) { uci->err = MC_IGNORED; uci->cksum = mc_header->rev; } else if (uci->err == MC_IGNORED && uci->cksum < mc_header->rev) uci->cksum = mc_header->rev; } else if (mc_header->rev == uci->rev) { if (uci->err < MC_MARKED) { /* notify the caller of success on this cpu */ uci->err = MC_SUCCESS; } } else if (uci->err != MC_ALLOCATED || mc_header->rev > uci->mc->hdr.rev) { pr_debug("microcode: CPU%d found a matching microcode update with " " revision 0x%x (current=0x%x)\n", cpu_num, mc_header->rev, uci->rev); uci->cksum = cksum; uci->pf = pf; /* keep the original mc pf for cksum calculation */ uci->err = MC_MARKED; /* found the match */ for_each_online_cpu(cpu_num) { if (ucode_cpu_info + cpu_num != uci && ucode_cpu_info[cpu_num].mc == uci->mc) { uci->mc = NULL; break; } } if (uci->mc != NULL) { vfree(uci->mc); uci->mc = NULL; } } return;}static int find_matching_ucodes (void) { int cursor = 0; int error = 0;
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