ivt.s

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	add	r2=TF_GREG16,r14
	add	r3=TF_GREG17,r14
	;;
	FILL_REG_PAIR(r16,r17,r2,r3)
	FILL_REG_PAIR(r18,r19,r2,r3)
	FILL_REG_PAIR(r20,r21,r2,r3)
	FILL_REG_PAIR(r22,r23,r2,r3)
	FILL_REG_PAIR(r24,r25,r2,r3)
	FILL_REG_PAIR(r26,r27,r2,r3)
	FILL_REG_PAIR(r28,r29,r2,r3)
	FILL_REG_PAIR(r30,r31,r2,r3)

	/*
	 * On XEN I have to store the bank 1 register into the
	 * global XSI_... area.
	 */
		// r16-r31 all now hold bank1 values
	movl r2=XSI_BANK1_R16
	movl r3=XSI_BANK1_R16+8
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r16=r16,@rev; mux1 r17=r17,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r16,16
	.mem.offset 8,0; st8.spill [r3]=r17,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r18=r18,@rev; mux1 r19=r19,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r18,16
	.mem.offset 8,0; st8.spill [r3]=r19,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r20=r20,@rev; mux1 r21=r21,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r20,16
	.mem.offset 8,0; st8.spill [r3]=r21,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r22=r22,@rev; mux1 r23=r23,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r22,16
	.mem.offset 8,0; st8.spill [r3]=r23,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r24=r24,@rev; mux1 r25=r25,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r24,16
	.mem.offset 8,0; st8.spill [r3]=r25,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r26=r26,@rev; mux1 r27=r27,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r26,16
	.mem.offset 8,0; st8.spill [r3]=r27,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r28=r28,@rev; mux1 r29=r29,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r28,16
	.mem.offset 8,0; st8.spill [r3]=r29,16
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r30=r30,@rev; mux1 r31=r31,@rev;;
#endif
	.mem.offset 0,0; st8.spill [r2]=r30,16
	.mem.offset 8,0; st8.spill [r3]=r31,16
	;;
	// bsw.0
	movl r2=XSI_BANKNUM;;
	st4 [r2]=r0;

	mov	r18=r14			// Move back the context pointer
	;;
	add	r19=TF_GREG2,r18
	add	r20=TF_GREG3,r18
	;;
	FILL_REG_PAIR( r2, r3,r19,r20)
	FILL_REG_PAIR( r8, r9,r19,r20)
	FILL_REG_PAIR(r10,r11,r19,r20)
	FILL_REG_PAIR(r14,r15,r19,r20)

	//// r18 - trap frame base, 

	add	r19=TF_CCV,r18
	add	r20=TF_CSD,r18
	;;
	ld8	r21=[r19]		// ar.ccv
	ld8	r22=[r20]		// ar.csd
	;;
	mov	ar.ccv=r21
	mov	ar.csd=r22
	add	r19=TF_SSD,r18
	;;
	ld8	r21=[r19]		// ar.ssd
	;;
	mov	ar.ssd=r21
	add	r19=TF_FREG6,r18
	add	r20=TF_FREG7,r18
	;;
	FILL_FP_PAIR(f6, f7, r19, r20)
	FILL_FP_PAIR(f8, f9, r19, r20)
	FILL_FP_PAIR(f10, f11, r19, r20)
	add	r19=TF_FPSR,r18
	;;
	ld8	r21=[r19]		// ar.fpsr
	;;
	mov	ar.fpsr=r21
	add	r19=TF_UNAT,r18
	;;
	ld8	r21=[r19]
	;;
	mov	ar.unat=r21
	;;
	srlz.i
	;;
	//rfi
	XEN_HYPER_RFI;
	;;
END(restore_tf_rse_switch)


ENTRY(save_special_regs)
	alloc	loc0=ar.pfs,1,7,0,0
	movl	loc1=XSI_IFA		// XEN !!
	movl	loc2=XSI_ISR		// XEN !!
	;;
	ld8	loc3=[loc1],XSI_IIM_OFS-XSI_IFA_OFS	// load XEN.ifa
	ld8	loc4=[loc2],XSI_IIPA_OFS-XSI_ISR_OFS	// load XEN.isr
	add	loc5=TF_IFA,in0
	add	loc6=TF_ISR,in0
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	loc3=loc3,@rev; mux1 loc4=loc4,@rev;;
#endif
	st8	[loc5]=loc3,TF_IIM-TF_IFA	// store cr.ifa
	st8	[loc6]=loc4			// store cr.isr
	;;
	ld8	loc3=[loc1]			// load XEN.iim
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	loc3=loc3,@rev;;
#endif
	st8	[loc5]=loc3			// store cr.iim
	;;
	mov	ar.pfs=loc0
	;;
	br.ret.sptk.few rp
END(save_special_regs)


ENTRY(hypervisor_callback)
	/*
	 * Use the thread stack here for storing the trap frame.
	 * It's not wired mapped, so nested data tlb faults may occur!
	 */
	add	r18=-TF_SIZE,sp
	;;
{	.mib
	nop	0x02
	mov	r16=ip		// for jump back from save_tf_rse_switch
	br.sptk	save_tf_rse_switch
	;;
}
	add	sp=-16,r18		// the new stack
	alloc	r15=ar.pfs,0,0,1,0	// 1 out for do_hypervisor_callback
	;;
	mov	out0=r18		// the trap frame
	movl	r22=XSI_PSR_IC
	mov	r23=1;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r23=r23,@rev;;
#endif
	st8	[r22]=r23		// ssm psr.ic
	;;
	br.call.sptk.few rp = do_hypervisor_callback

	movl	r22=XSI_PSR_IC
	;;
	st4	[r22]=r0		// rsm psr.ic
	add	r18=16,sp		// load EF-pointer again
	;;
			// must have r18-efp, calls rfi at the end.
	br.sptk	restore_tf_rse_switch
	;;
END(hypervisor_callback)

	/*
	 * In: r30 - trap number
	 */
ENTRY(trap_error)
		// Calculate the stack address for storing.
	add	r18=-TF_SIZE,sp
	;;
	add	r20=TF_TRAP_NUM,r18
	;;
	st2	[r20]=r30	// save trap number
	;;

{	.mib
	nop	0x02
	mov	r16=ip		// for jumping back from save_tf_rse_switch
		// Used register: r16, r18, r19, r20, r21, r22 of bank 0
	br.sptk	save_tf_rse_switch
	;;
}

	alloc	r15=ar.pfs,0,0,1,0	// 1 out for do_trap_error
	;;
	mov	out0=r18		// the trap frame
	add	sp=-16,r18		// C-call abi
	;;
	movl r30=XSI_BANKNUM		// bsw.1
	mov r31=1;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r31=r31,@rev;;
#endif
	st4 [r30]=r31;;

		/* Save extra interrupt registers to the trap frame. */
	br.call.sptk.few rp = save_special_regs
	;;

	movl	r22=XSI_PSR_IC
	movl	r23=XSI_PSR_I_ADDR
	;;
	ld8	r23=[r23]
	mov	r25=1
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r25=r25,@rev; mux1 r23=r23,@rev;;
#endif
	st4	[r22]=r25		// ssm psr.ic
	st1	[r23]=r0		// ssm psr.i
	;;

	br.call.sptk.few rp = do_trap_error
	;;
		// --> currently not reached!!!
	movl r23=XSI_PSR_I_ADDR
	movl r22=XSI_PSR_IC
	;;
	ld8 r23=[r23]
	mov r25=1
	;;
#if defined(BIG_ENDIAN)			// swap because mini-os is in BE
	mux1	r25=r25,@rev;;
	mux1	r25=r25,@rev; mux1 r23=r23,@rev;;
#endif
	st1 [r23]=r25
	st4 [r22]=r0            // note: clears both vpsr.i and vpsr.ic!
	;;
	bsw.0
	;;
	add	r18=16,sp		// load EF-pointer again
	;;
	mov	sp=r18
			// must have r18-efp, calls rfi at the end.
	br.sptk	restore_tf_rse_switch
	;;
END(trap_error)


/*
 * The trap handler stuff.
 */

#define TRAP_ERR(num)			\
	mov	r30 = num;		\
	;;		;		\
	br.sptk	trap_error		\
	;;

#define	IVT_ENTRY(name, offset)			\
	.org	ia64_trap_table + offset;	\
	.global	hivt_##name;			\
	.proc	hivt_##name;			\
	.prologue;				\
	.body;					\
hivt_##name:

#define	IVT_END(name)				\
	.endp	hivt_##name;			\
	.align	0x100

#define IVT_ERR(name, num, offset)		\
	IVT_ENTRY(name, offset);		\
	TRAP_ERR(num);				\
	IVT_END(name)
/*
 * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64
 * bundles per vector and 48 slots with 16 bundles per vector.
 */

	.section .text.hivt,"ax"
	.align	32768
	.global ia64_trap_table
	.size	ia64_trap_table, 32768
ia64_trap_table:

IVT_ERR(VHPT_Translation, 0, 0x0)
IVT_ERR(Instruction_TLB, 1, 0x0400)
IVT_ERR(Data_TLB, 2, 0x0800)
IVT_ERR(Alternate_Instruction_TLB, 3, 0x0c00)


IVT_ENTRY(Alternate_Data_TLB, 0x1000)
	mov	r30=4			// trap number
adt_common:
	mov	r16=cr.ifa		// where did it happen
	mov	r31=pr			// save predicates
	;;
	extr.u	r17=r16,IA64_RR_IDX_POS,3	// get region number
	;;
	cmp.eq	p14,p15=7,r17
	;;
//(p14)	br.sptk adt_regf_addr		// Check for region 7 - phys addresses
//	;;
//	br.sptk	trap_error
//		// No return
//
//adt_regf_addr:
//	extr.u	r17=r16,60,4		// get region number
//	;;
//	cmp.eq	p14,p15=0xf,r17
//	;;
(p14)	br.sptk adt_reg7_addr		// Check for region 7 - phys addresses
	;;
	br.sptk	trap_error

adt_reg7_addr:
	/*
	 * region 7 addresses are only directly mapped physically
	 * addresses. Currently I don't do a check.
	 */
	movl	r20=~((7 << IA64_RR_IDX_POS) | 0xfff)
	movl	r18=((PTE_PS_16K<<IA64_ITIR_PS)|(IA64_KEY_REG7<<IA64_ITIR_KEY))
	;;
	movl	r19=	((1<<PTE_OFF_P) | (PTE_MA_WB<<PTE_OFF_MA) | \
			 (1<<PTE_OFF_A) | (1<<PTE_OFF_D) | \
			 (PTE_PL_KERN<<PTE_OFF_PL) | (PTE_AR_RW<<PTE_OFF_AR))
			// clear the region bits and 0-11
			// extract the pfn from the ifa
	mov	cr.itir=r18
	and	r20=r20, r16
	;;
	or	r20=r20,r19		// put pfn into pte
	;;
	mov	pr=r31,-1		// restore predicates
	itc.d	r20
	;;
	XEN_HYPER_RFI;
	;;

IVT_END(Alternate_Data_TLB)

/*
 * Handling of nested data tlb is needed, because in hypervisor_callback()
 * the stack is used to store the register trap frame. This stack is allocated
 * dynamically (as identity mapped address) and therewidth no tr mapped page!
 */
IVT_ENTRY(Data_Nested_TLB, 0x1400)

	mov	r30=5			// trap number
	add	r28=-TF_SIZE,sp		// r28 is never used in trap handling
	;;
	mov	cr.ifa=r28
	;;
	br.sptk	adt_common
IVT_END(Data_Nested_TLB)



IVT_ERR(Instruction_Key_Miss, 6, 0x1800)
IVT_ERR(Data_Key_Miss, 7, 0x1c00)
IVT_ERR(Dirty_Bit, 8, 0x2000)
IVT_ERR(Instruction_Access_Bit, 9, 0x2400)
IVT_ERR(Data_Access_Bit, 10, 0x2800)
IVT_ERR(Break_Instruction, 11, 0x2c00)
IVT_ERR(External_Interrupt, 12, 0x3000)
IVT_ERR(Reserved_3400, 13, 0x3400)
IVT_ERR(Reserved_3800, 14, 0x3800)
IVT_ERR(Reserved_3c00, 15, 0x3c00)
IVT_ERR(Reserved_4000, 16, 0x4000)
IVT_ERR(Reserved_4400, 17, 0x4400)
IVT_ERR(Reserved_4800, 18, 0x4800)
IVT_ERR(Reserved_4c00, 19, 0x4c00)
IVT_ERR(Page_Not_Present, 20, 0x5000)
IVT_ERR(Key_Permission, 21, 0x5100)
IVT_ERR(Instruction_Access_Rights, 22, 0x5200)
IVT_ERR(Data_Access_Rights, 23, 0x5300)
IVT_ERR(General_Exception, 24, 0x5400)
IVT_ERR(Disabled_FP_Register, 25, 0x5500)
IVT_ERR(NaT_Consumption, 26, 0x5600)
IVT_ERR(Speculation, 27, 0x5700)
IVT_ERR(Reserved_5800, 28, 0x5800)
IVT_ERR(Debug, 29, 0x5900)
IVT_ERR(Unaligned_Reference, 30, 0x5a00)
IVT_ERR(Unsupported_Data_Reference, 31, 0x5b00)
IVT_ERR(Floating_Point_Fault, 32, 0x5c00)
IVT_ERR(Floating_Point_Trap, 33, 0x5d00)
IVT_ERR(Lower_Privilege_Transfer_Trap, 34, 0x5e00)
IVT_ERR(Taken_Branch_Trap, 35, 0x5f00)
IVT_ERR(Single_Step_Trap, 36, 0x6000)
IVT_ERR(Reserved_6100, 37, 0x6100)
IVT_ERR(Reserved_6200, 38, 0x6200)
IVT_ERR(Reserved_6300, 39, 0x6300)
IVT_ERR(Reserved_6400, 40, 0x6400)
IVT_ERR(Reserved_6500, 41, 0x6500)
IVT_ERR(Reserved_6600, 42, 0x6600)
IVT_ERR(Reserved_6700, 43, 0x6700)
IVT_ERR(Reserved_6800, 44, 0x6800)
IVT_ERR(IA_32_Exception, 45, 0x6900)
IVT_ERR(IA_32_Intercept, 46, 0x6a00)
IVT_ERR(IA_32_Interrupt, 47, 0x6b00)
IVT_ERR(Reserved_6c00, 48, 0x6c00)
IVT_ERR(Reserved_6d00, 49, 0x6d00)
IVT_ERR(Reserved_6e00, 50, 0x6e00)
IVT_ERR(Reserved_6f00, 51, 0x6f00)
IVT_ERR(Reserved_7000, 52, 0x7000)
IVT_ERR(Reserved_7100, 53, 0x7100)
IVT_ERR(Reserved_7200, 54, 0x7200)
IVT_ERR(Reserved_7300, 55, 0x7300)
IVT_ERR(Reserved_7400, 56, 0x7400)
IVT_ERR(Reserved_7500, 57, 0x7500)
IVT_ERR(Reserved_7600, 58, 0x7600)
IVT_ERR(Reserved_7700, 59, 0x7700)
IVT_ERR(Reserved_7800, 60, 0x7800)
IVT_ERR(Reserved_7900, 61, 0x7900)
IVT_ERR(Reserved_7a00, 62, 0x7a00)
IVT_ERR(Reserved_7b00, 63, 0x7b00)
IVT_ERR(Reserved_7c00, 64, 0x7c00)
IVT_ERR(Reserved_7d00, 65, 0x7d00)
IVT_ERR(Reserved_7e00, 66, 0x7e00)
IVT_ERR(Reserved_7f00, 67, 0x7f00)