op.c

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}

void op_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
    FORCE_RET();
}

void op_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
    FORCE_RET();
}

/* Multiplication variants of the vr54xx. */
void op_muls (void)
{
    set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_mulsu (void)
{
    set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_macc (void)
{
    set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_macchi (void)
{
    set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_maccu (void)
{
    set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_macchiu (void)
{
    set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_msac (void)
{
    set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_msachi (void)
{
    set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_msacu (void)
{
    set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_msachiu (void)
{
    set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

void op_mulhi (void)
{
    set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    FORCE_RET();
}

void op_mulhiu (void)
{
    set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    FORCE_RET();
}

void op_mulshi (void)
{
    set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
    FORCE_RET();
}

void op_mulshiu (void)
{
    set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
    FORCE_RET();
}

#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

#if defined(TARGET_MIPS64)
void op_dmult (void)
{
    CALL_FROM_TB4(muls64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
    FORCE_RET();
}

void op_dmultu (void)
{
    CALL_FROM_TB4(mulu64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
    FORCE_RET();
}
#endif

/* Conditional moves */
void op_movn (void)
{
    if (T1 != 0)
        env->gpr[env->current_tc][PARAM1] = T0;
    FORCE_RET();
}

void op_movz (void)
{
    if (T1 == 0)
        env->gpr[env->current_tc][PARAM1] = T0;
    FORCE_RET();
}

void op_movf (void)
{
    if (!(env->fpu->fcr31 & PARAM1))
        T0 = T1;
    FORCE_RET();
}

void op_movt (void)
{
    if (env->fpu->fcr31 & PARAM1)
        T0 = T1;
    FORCE_RET();
}

/* Tests */
#define OP_COND(name, cond) \
void glue(op_, name) (void) \
{                           \
    if (cond) {             \
        T0 = 1;             \
    } else {                \
        T0 = 0;             \
    }                       \
    FORCE_RET();            \
}

OP_COND(eq, T0 == T1);
OP_COND(ne, T0 != T1);
OP_COND(ge, (target_long)T0 >= (target_long)T1);
OP_COND(geu, T0 >= T1);
OP_COND(lt, (target_long)T0 < (target_long)T1);
OP_COND(ltu, T0 < T1);
OP_COND(gez, (target_long)T0 >= 0);
OP_COND(gtz, (target_long)T0 > 0);
OP_COND(lez, (target_long)T0 <= 0);
OP_COND(ltz, (target_long)T0 < 0);

/* Branches */
/* Branch to register */
void op_save_breg_target (void)
{
    env->btarget = T1;
    FORCE_RET();
}

void op_breg (void)
{
    env->PC[env->current_tc] = env->btarget;
    FORCE_RET();
}

void op_save_btarget (void)
{
    env->btarget = PARAM1;
    FORCE_RET();
}

#if defined(TARGET_MIPS64)
void op_save_btarget64 (void)
{
    env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
    FORCE_RET();
}
#endif

/* Conditional branch */
void op_set_bcond (void)
{
    env->bcond = T0;
    FORCE_RET();
}

void op_jnz_bcond (void)
{
    if (env->bcond)
        GOTO_LABEL_PARAM(1);
    FORCE_RET();
}

/* CP0 functions */
void op_mfc0_index (void)
{
    T0 = env->CP0_Index;
    FORCE_RET();
}

void op_mfc0_mvpcontrol (void)
{
    T0 = env->mvp->CP0_MVPControl;
    FORCE_RET();
}

void op_mfc0_mvpconf0 (void)
{
    T0 = env->mvp->CP0_MVPConf0;
    FORCE_RET();
}

void op_mfc0_mvpconf1 (void)
{
    T0 = env->mvp->CP0_MVPConf1;
    FORCE_RET();
}

void op_mfc0_random (void)
{
    CALL_FROM_TB0(do_mfc0_random);
    FORCE_RET();
}

void op_mfc0_vpecontrol (void)
{
    T0 = env->CP0_VPEControl;
    FORCE_RET();
}

void op_mfc0_vpeconf0 (void)
{
    T0 = env->CP0_VPEConf0;
    FORCE_RET();
}

void op_mfc0_vpeconf1 (void)
{
    T0 = env->CP0_VPEConf1;
    FORCE_RET();
}

void op_mfc0_yqmask (void)
{
    T0 = env->CP0_YQMask;
    FORCE_RET();
}

void op_mfc0_vpeschedule (void)
{
    T0 = env->CP0_VPESchedule;
    FORCE_RET();
}

void op_mfc0_vpeschefback (void)
{
    T0 = env->CP0_VPEScheFBack;
    FORCE_RET();
}

void op_mfc0_vpeopt (void)
{
    T0 = env->CP0_VPEOpt;
    FORCE_RET();
}

void op_mfc0_entrylo0 (void)
{
    T0 = (int32_t)env->CP0_EntryLo0;
    FORCE_RET();
}

void op_mfc0_tcstatus (void)
{
    T0 = env->CP0_TCStatus[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcstatus(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCStatus[other_tc];
    FORCE_RET();
}

void op_mfc0_tcbind (void)
{
    T0 = env->CP0_TCBind[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcbind(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCBind[other_tc];
    FORCE_RET();
}

void op_mfc0_tcrestart (void)
{
    T0 = env->PC[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcrestart(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->PC[other_tc];
    FORCE_RET();
}

void op_mfc0_tchalt (void)
{
    T0 = env->CP0_TCHalt[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tchalt(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCHalt[other_tc];
    FORCE_RET();
}

void op_mfc0_tccontext (void)
{
    T0 = env->CP0_TCContext[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tccontext(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCContext[other_tc];
    FORCE_RET();
}

void op_mfc0_tcschedule (void)
{
    T0 = env->CP0_TCSchedule[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcschedule(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCSchedule[other_tc];
    FORCE_RET();
}

void op_mfc0_tcschefback (void)
{
    T0 = env->CP0_TCScheFBack[env->current_tc];
    FORCE_RET();
}

void op_mftc0_tcschefback(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCScheFBack[other_tc];
    FORCE_RET();
}

void op_mfc0_entrylo1 (void)
{
    T0 = (int32_t)env->CP0_EntryLo1;
    FORCE_RET();
}

void op_mfc0_context (void)
{
    T0 = (int32_t)env->CP0_Context;
    FORCE_RET();
}

void op_mfc0_pagemask (void)
{
    T0 = env->CP0_PageMask;
    FORCE_RET();
}

void op_mfc0_pagegrain (void)
{
    T0 = env->CP0_PageGrain;
    FORCE_RET();
}

void op_mfc0_wired (void)
{
    T0 = env->CP0_Wired;
    FORCE_RET();
}

void op_mfc0_srsconf0 (void)
{
    T0 = env->CP0_SRSConf0;
    FORCE_RET();
}

void op_mfc0_srsconf1 (void)
{
    T0 = env->CP0_SRSConf1;
    FORCE_RET();
}

void op_mfc0_srsconf2 (void)
{
    T0 = env->CP0_SRSConf2;
    FORCE_RET();
}

void op_mfc0_srsconf3 (void)
{
    T0 = env->CP0_SRSConf3;
    FORCE_RET();
}

void op_mfc0_srsconf4 (void)
{
    T0 = env->CP0_SRSConf4;
    FORCE_RET();
}

void op_mfc0_hwrena (void)
{
    T0 = env->CP0_HWREna;
    FORCE_RET();
}

void op_mfc0_badvaddr (void)
{
    T0 = (int32_t)env->CP0_BadVAddr;
    FORCE_RET();
}

void op_mfc0_count (void)
{
    CALL_FROM_TB0(do_mfc0_count);
    FORCE_RET();
}

void op_mfc0_entryhi (void)
{
    T0 = (int32_t)env->CP0_EntryHi;
    FORCE_RET();
}

void op_mftc0_entryhi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
    FORCE_RET();
}

void op_mfc0_compare (void)
{
    T0 = env->CP0_Compare;
    FORCE_RET();
}

void op_mfc0_status (void)
{
    T0 = env->CP0_Status;
    FORCE_RET();
}

void op_mftc0_status(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];

    T0 = env->CP0_Status & ~0xf1000018;
    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
    FORCE_RET();
}

void op_mfc0_intctl (void)
{
    T0 = env->CP0_IntCtl;
    FORCE_RET();
}

void op_mfc0_srsctl (void)
{
    T0 = env->CP0_SRSCtl;
    FORCE_RET();
}

void op_mfc0_srsmap (void)
{
    T0 = env->CP0_SRSMap;
    FORCE_RET();
}

void op_mfc0_cause (void)
{
    T0 = env->CP0_Cause;
    FORCE_RET();
}

void op_mfc0_epc (void)
{
    T0 = (int32_t)env->CP0_EPC;
    FORCE_RET();
}

void op_mfc0_prid (void)
{
    T0 = env->CP0_PRid;
    FORCE_RET();
}

void op_mfc0_ebase (void)
{
    T0 = env->CP0_EBase;
    FORCE_RET();
}

void op_mfc0_config0 (void)
{
    T0 = env->CP0_Config0;
    FORCE_RET();
}

void op_mfc0_config1 (void)
{
    T0 = env->CP0_Config1;
    FORCE_RET();
}

void op_mfc0_config2 (void)
{
    T0 = env->CP0_Config2;
    FORCE_RET();
}

void op_mfc0_config3 (void)
{
    T0 = env->CP0_Config3;
    FORCE_RET();
}

void op_mfc0_config6 (void)
{
    T0 = env->CP0_Config6;
    FORCE_RET();
}

void op_mfc0_config7 (void)
{
    T0 = env->CP0_Config7;
    FORCE_RET();
}

void op_mfc0_lladdr (void)
{
    T0 = (int32_t)env->CP0_LLAddr >> 4;
    FORCE_RET();
}

void op_mfc0_watchlo (void)
{
    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
    FORCE_RET();
}

void op_mfc0_watchhi (void)
{
    T0 = env->CP0_WatchHi[PARAM1];
    FORCE_RET();
}

void op_mfc0_xcontext (void)
{
    T0 = (int32_t)env->CP0_XContext;
    FORCE_RET();
}

void op_mfc0_framemask (void)
{
    T0 = env->CP0_Framemask;
    FORCE_RET();
}

void op_mfc0_debug (void)
{
    T0 = env->CP0_Debug;
    if (env->hflags & MIPS_HFLAG_DM)
        T0 |= 1 << CP0DB_DM;
    FORCE_RET();
}

void op_mftc0_debug(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    /* XXX: Might be wrong, check with EJTAG spec. */
    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
         (env->CP0_Debug_tcstatus[other_tc] &
          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
    FORCE_RET();
}

void op_mfc0_depc (void)
{
    T0 = (int32_t)env->CP0_DEPC;
    FORCE_RET();
}

void op_mfc0_performance0 (void)
{
    T0 = env->CP0_Performance0;
    FORCE_RET();
}

void op_mfc0_taglo (void)
{
    T0 = env->CP0_TagLo;
    FORCE_RET();
}

void op_mfc0_datalo (void)
{
    T0 = env->CP0_DataLo;
    FORCE_RET();
}

void op_mfc0_taghi (void)
{
    T0 = env->CP0_TagHi;
    FORCE_RET();
}

void op_mfc0_datahi (void)
{
    T0 = env->CP0_DataHi;
    FORCE_RET();
}

void op_mfc0_errorepc (void)
{
    T0 = (int32_t)env->CP0_ErrorEPC;
    FORCE_RET();
}

void op_mfc0_desave (void)
{
    T0 = env->CP0_DESAVE;
    FORCE_RET();
}

void op_mtc0_index (void)
{
    int num = 1;
    unsigned int tmp = env->tlb->nb_tlb;

    do {
        tmp >>= 1;
        num <<= 1;
    } while (tmp);
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
    FORCE_RET();
}

void op_mtc0_mvpcontrol (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
        mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
                (1 << CP0MVPCo_EVP);
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0MVPCo_STLB);
    newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);

    // TODO: Enable/disable shared TLB, enable/disable VPEs.

    env->mvp->CP0_MVPControl = newval;
    FORCE_RET();
}

void op_mtc0_vpecontrol (void)
{
    uint32_t mask;
    uint32_t newval;

    mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
           (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
    newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);

    /* Yield scheduler intercept not implemented. */
    /* Gating storage scheduler intercept not implemented. */

    // TODO: Enable/disable TCs.

    env->CP0_VPEControl = newval;
    FORCE_RET();
}

void op_mtc0_vpeconf0 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
        if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
            mask |= (0xff << CP0VPEC0_XTC);
        mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
    }
    newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);

    // TODO: TC exclusive handling due to ERL/EXL.

    env->CP0_VPEConf0 = newval;
    FORCE_RET();
}

void op_mtc0_vpeconf1 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                (0xff << CP0VPEC1_NCP1);
    newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);

    /* UDI not implemented. */
    /* CP2 not implemented. */

    // TODO: Handle FPU (CP1) binding.

    env->CP0_VPEConf1 = newval;
    FORCE_RET();
}

void op_mtc0_yqmask (void)
{
    /* Yield qualifier inputs not implemented. */
    env->CP0_YQMask = 0x00000000;
    FORCE_RET();
}

void op_mtc0_vpeschedule (void)
{
    env->CP0_VPESchedule = T0;
    FORCE_RET();
}

void op_mtc0_vpeschefback (void)
{
    env->CP0_VPEScheFBack = T0;
    FORCE_RET();
}

void op_mtc0_vpeopt (void)
{
    env->CP0_VPEOpt = T0 & 0x0000ffff;
    FORCE_RET();
}