tcg-op.h

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    tcg_gen_shri_i32(t1, arg, 8);
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
    tcg_gen_or_i32(t0, t0, t1);
    
    tcg_gen_shri_i32(t1, arg, 24);
    tcg_gen_or_i32(ret, t0, t1);
#endif
}

#if TCG_TARGET_REG_BITS == 32
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
{
    tcg_gen_ext8s_i32(ret, arg);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
}

static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
{
    tcg_gen_ext16s_i32(ret, arg);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
}

static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
}

static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_ext8u_i32(ret, arg);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}

static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_ext16u_i32(ret, arg);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}

static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}

static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
}

static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}

static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
}

static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
{
    TCGv t0, t1;
    t0 = tcg_temp_new(TCG_TYPE_I32);
    t1 = tcg_temp_new(TCG_TYPE_I32);

    tcg_gen_bswap_i32(t0, arg);
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
    tcg_gen_mov_i32(ret, t1);
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
}
#else

static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_ext8s_i64
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
#else
    tcg_gen_shli_i64(ret, arg, 56);
    tcg_gen_sari_i64(ret, ret, 56);
#endif
}

static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_ext16s_i64
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
#else
    tcg_gen_shli_i64(ret, arg, 48);
    tcg_gen_sari_i64(ret, ret, 48);
#endif
}

static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_ext32s_i64
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
#else
    tcg_gen_shli_i64(ret, arg, 32);
    tcg_gen_sari_i64(ret, ret, 32);
#endif
}

static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_andi_i64(ret, arg, 0xffu);
}

static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_andi_i64(ret, arg, 0xffffu);
}

static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
{
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
}

/* Note: we assume the target supports move between 32 and 64 bit
   registers.  This will probably break MIPS64 targets.  */
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
{
    tcg_gen_mov_i32(ret, arg);
}

/* Note: we assume the target supports move between 32 and 64 bit
   registers */
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
{
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
}

/* Note: we assume the target supports move between 32 and 64 bit
   registers */
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
{
    tcg_gen_ext32s_i64(ret, arg);
}

static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_bswap_i64
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
#else
    TCGv t0, t1;
    t0 = tcg_temp_new(TCG_TYPE_I32);
    t1 = tcg_temp_new(TCG_TYPE_I32);
    
    tcg_gen_shli_i64(t0, arg, 56);
    
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
    tcg_gen_shli_i64(t1, t1, 40);
    tcg_gen_or_i64(t0, t0, t1);
    
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
    tcg_gen_shli_i64(t1, t1, 24);
    tcg_gen_or_i64(t0, t0, t1);

    tcg_gen_andi_i64(t1, arg, 0xff000000);
    tcg_gen_shli_i64(t1, t1, 8);
    tcg_gen_or_i64(t0, t0, t1);

    tcg_gen_shri_i64(t1, arg, 8);
    tcg_gen_andi_i64(t1, t1, 0xff000000);
    tcg_gen_or_i64(t0, t0, t1);
    
    tcg_gen_shri_i64(t1, arg, 24);
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
    tcg_gen_or_i64(t0, t0, t1);

    tcg_gen_shri_i64(t1, arg, 40);
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
    tcg_gen_or_i64(t0, t0, t1);

    tcg_gen_shri_i64(t1, arg, 56);
    tcg_gen_or_i64(ret, t0, t1);
#endif
}

#endif

static inline void tcg_gen_neg_i32(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_neg_i32
    tcg_gen_op2(INDEX_op_neg_i32, ret, arg);
#else
    tcg_gen_sub_i32(ret, tcg_const_i32(0), arg);
#endif
}

static inline void tcg_gen_neg_i64(TCGv ret, TCGv arg)
{
#ifdef TCG_TARGET_HAS_neg_i64
    tcg_gen_op2(INDEX_op_neg_i64, ret, arg);
#else
    tcg_gen_sub_i64(ret, tcg_const_i64(0), arg);
#endif
}


static inline void tcg_gen_discard_i32(TCGv arg)
{
    tcg_gen_op1(INDEX_op_discard, arg);
}

#if TCG_TARGET_REG_BITS == 32
static inline void tcg_gen_discard_i64(TCGv arg)
{
    tcg_gen_discard_i32(arg);
    tcg_gen_discard_i32(TCGV_HIGH(arg));
}
#else
static inline void tcg_gen_discard_i64(TCGv arg)
{
    tcg_gen_op1(INDEX_op_discard, arg);
}
#endif

/***************************************/
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
{
    tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id);
}

/***************************************/
/* QEMU specific operations. Their type depend on the QEMU CPU
   type. */
#ifndef TARGET_LONG_BITS
#error must include QEMU headers
#endif

static inline void tcg_gen_exit_tb(tcg_target_long val)
{
    tcg_gen_op1i(INDEX_op_exit_tb, val);
}

static inline void tcg_gen_goto_tb(int idx)
{
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
}

#if TCG_TARGET_REG_BITS == 32
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
#endif
}

static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
#endif
}

static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
#endif
}

static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
#endif
}

static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
#endif
}

static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
#endif
}

static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
#else
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
                 addr, TCGV_HIGH(addr), mem_index);
#endif
}

static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
#endif
}

static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
#endif
}

static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
#else
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
#endif
}

static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
#else
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
                 addr, TCGV_HIGH(addr), mem_index);
#endif
}

#define tcg_gen_ld_ptr tcg_gen_ld_i32
#define tcg_gen_discard_ptr tcg_gen_discard_i32

#else /* TCG_TARGET_REG_BITS == 32 */

static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
}

static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
}

static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
}

static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
}

static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
{
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
}

#define tcg_gen_ld_ptr tcg_gen_ld_i64
#define tcg_gen_discard_ptr tcg_gen_discard_i64

#endif /* TCG_TARGET_REG_BITS != 32 */

#if TARGET_LONG_BITS == 64
#define TCG_TYPE_TL TCG_TYPE_I64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
#define tcg_gen_ld_tl tcg_gen_ld_i64
#define tcg_gen_st8_tl tcg_gen_st8_i64
#define tcg_gen_st16_tl tcg_gen_st16_i64
#define tcg_gen_st32_tl tcg_gen_st32_i64
#define tcg_gen_st_tl tcg_gen_st_i64
#define tcg_gen_add_tl tcg_gen_add_i64
#define tcg_gen_addi_tl tcg_gen_addi_i64
#define tcg_gen_sub_tl tcg_gen_sub_i64
#define tcg_gen_neg_tl tcg_gen_neg_i64
#define tcg_gen_subi_tl tcg_gen_subi_i64
#define tcg_gen_and_tl tcg_gen_and_i64
#define tcg_gen_andi_tl tcg_gen_andi_i64
#define tcg_gen_or_tl tcg_gen_or_i64
#define tcg_gen_ori_tl tcg_gen_ori_i64
#define tcg_gen_xor_tl tcg_gen_xor_i64
#define tcg_gen_xori_tl tcg_gen_xori_i64
#define tcg_gen_shl_tl tcg_gen_shl_i64
#define tcg_gen_shli_tl tcg_gen_shli_i64
#define tcg_gen_shr_tl tcg_gen_shr_i64
#define tcg_gen_shri_tl tcg_gen_shri_i64
#define tcg_gen_sar_tl tcg_gen_sar_i64
#define tcg_gen_sari_tl tcg_gen_sari_i64
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
#define tcg_gen_mul_tl tcg_gen_mul_i64
#define tcg_gen_muli_tl tcg_gen_muli_i64
#define tcg_gen_discard_tl tcg_gen_discard_i64
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
#define tcg_const_tl tcg_const_i64
#else
#define TCG_TYPE_TL TCG_TYPE_I32
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
#define tcg_gen_ld_tl tcg_gen_ld_i32
#define tcg_gen_st8_tl tcg_gen_st8_i32
#define tcg_gen_st16_tl tcg_gen_st16_i32
#define tcg_gen_st32_tl tcg_gen_st_i32
#define tcg_gen_st_tl tcg_gen_st_i32
#define tcg_gen_add_tl tcg_gen_add_i32
#define tcg_gen_addi_tl tcg_gen_addi_i32
#define tcg_gen_sub_tl tcg_gen_sub_i32
#define tcg_gen_neg_tl tcg_gen_neg_i32
#define tcg_gen_subi_tl tcg_gen_subi_i32
#define tcg_gen_and_tl tcg_gen_and_i32
#define tcg_gen_andi_tl tcg_gen_andi_i32
#define tcg_gen_or_tl tcg_gen_or_i32
#define tcg_gen_ori_tl tcg_gen_ori_i32
#define tcg_gen_xor_tl tcg_gen_xor_i32
#define tcg_gen_xori_tl tcg_gen_xori_i32
#define tcg_gen_shl_tl tcg_gen_shl_i32
#define tcg_gen_shli_tl tcg_gen_shli_i32
#define tcg_gen_shr_tl tcg_gen_shr_i32
#define tcg_gen_shri_tl tcg_gen_shri_i32
#define tcg_gen_sar_tl tcg_gen_sar_i32
#define tcg_gen_sari_tl tcg_gen_sari_i32
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
#define tcg_gen_mul_tl tcg_gen_mul_i32
#define tcg_gen_muli_tl tcg_gen_muli_i32
#define tcg_gen_discard_tl tcg_gen_discard_i32
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
#define tcg_const_tl tcg_const_i32
#endif

#if TCG_TARGET_REG_BITS == 32
#define tcg_gen_addi_ptr tcg_gen_addi_i32
#else /* TCG_TARGET_REG_BITS == 32 */
#define tcg_gen_addi_ptr tcg_gen_addi_i64
#endif /* TCG_TARGET_REG_BITS != 32 */