translate.c

来自「xen虚拟机源代码安装包」· C语言 代码 · 共 1,317 行 · 第 1/3 页

	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x6008:		/* swap.b Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_swapb_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x6009:		/* swap.w Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_swapw_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x200d:		/* xtrct Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_xtrct_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x300c:		/* add Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_add_T0_rN(REG(B11_8));
	return;
    case 0x300e:		/* addc Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_addc_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x300f:		/* addv Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_addv_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x2009:		/* and Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_and_T0_rN(REG(B11_8));
	return;
    case 0x3000:		/* cmp/eq Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_eq_T0_T1();
	return;
    case 0x3003:		/* cmp/ge Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_ge_T0_T1();
	return;
    case 0x3007:		/* cmp/gt Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_gt_T0_T1();
	return;
    case 0x3006:		/* cmp/hi Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_hi_T0_T1();
	return;
    case 0x3002:		/* cmp/hs Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_hs_T0_T1();
	return;
    case 0x200c:		/* cmp/str Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_cmp_str_T0_T1();
	return;
    case 0x2007:		/* div0s Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_div0s_T0_T1();
	return;
    case 0x3004:		/* div1 Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_div1_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x300d:		/* dmuls.l Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_dmulsl_T0_T1();
	return;
    case 0x3005:		/* dmulu.l Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_dmulul_T0_T1();
	return;
    case 0x600e:		/* exts.b Rm,Rn */
	gen_op_movb_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600f:		/* exts.w Rm,Rn */
	gen_op_movw_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600c:		/* extu.b Rm,Rn */
	gen_op_movub_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600d:		/* extu.w Rm,Rn */
	gen_op_movuw_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x000f:		/* mac.l @Rm+,@Rn+ */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_T1();
	gen_op_inc4_rN(REG(B11_8));
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_ldl_T0_T0(ctx);
	gen_op_macl_T0_T1();
	gen_op_inc4_rN(REG(B7_4));
	return;
    case 0x400f:		/* mac.w @Rm+,@Rn+ */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_T1();
	gen_op_inc2_rN(REG(B11_8));
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_ldl_T0_T0(ctx);
	gen_op_macw_T0_T1();
	gen_op_inc2_rN(REG(B7_4));
	return;
    case 0x0007:		/* mul.l Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_mull_T0_T1();
	return;
    case 0x200f:		/* muls.w Rm,Rn */
	gen_op_movw_rN_T0(REG(B7_4));
	gen_op_movw_rN_T1(REG(B11_8));
	gen_op_mulsw_T0_T1();
	return;
    case 0x200e:		/* mulu.w Rm,Rn */
	gen_op_movuw_rN_T0(REG(B7_4));
	gen_op_movuw_rN_T1(REG(B11_8));
	gen_op_muluw_T0_T1();
	return;
    case 0x600b:		/* neg Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_neg_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600a:		/* negc Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_negc_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x6007:		/* not Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_not_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x200b:		/* or Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_or_T0_rN(REG(B11_8));
	return;
    case 0x400c:		/* shad Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_shad_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x400d:		/* shld Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_shld_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x3008:		/* sub Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_sub_T0_rN(REG(B11_8));
	return;
    case 0x300a:		/* subc Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_subc_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x300b:		/* subv Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_subv_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x2008:		/* tst Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_tst_T0_T1();
	return;
    case 0x200a:		/* xor Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_xor_T0_rN(REG(B11_8));
	return;
    case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_fmov_drN_DT0(XREG(B7_4));
	    gen_op_fmov_DT0_drN(XREG(B11_8));
	} else {
	    gen_op_fmov_frN_FT0(FREG(B7_4));
	    gen_op_fmov_FT0_frN(FREG(B11_8));
	}
	return;
    case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_fmov_drN_DT0(XREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_stfq_DT0_T1(ctx);
	} else {
	    gen_op_fmov_frN_FT0(FREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_stfl_FT0_T1(ctx);
	}
	return;
    case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_ldfq_T0_DT0(ctx);
	    gen_op_fmov_DT0_drN(XREG(B11_8));
	} else {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_ldfl_T0_FT0(ctx);
	    gen_op_fmov_FT0_frN(FREG(B11_8));
	}
	return;
    case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_ldfq_T0_DT0(ctx);
	    gen_op_fmov_DT0_drN(XREG(B11_8));
	    gen_op_inc8_rN(REG(B7_4));
	} else {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_ldfl_T0_FT0(ctx);
	    gen_op_fmov_FT0_frN(FREG(B11_8));
	    gen_op_inc4_rN(REG(B7_4));
	}
	return;
    case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_dec8_rN(REG(B11_8));
	    gen_op_fmov_drN_DT0(XREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_stfq_DT0_T1(ctx);
	} else {
	    gen_op_dec4_rN(REG(B11_8));
	    gen_op_fmov_frN_FT0(FREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_stfl_FT0_T1(ctx);
	}
	return;
    case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_add_rN_T0(REG(0));
	    gen_op_ldfq_T0_DT0(ctx);
	    gen_op_fmov_DT0_drN(XREG(B11_8));
	} else {
	    gen_op_movl_rN_T0(REG(B7_4));
	    gen_op_add_rN_T0(REG(0));
	    gen_op_ldfl_T0_FT0(ctx);
	    gen_op_fmov_FT0_frN(FREG(B11_8));
	}
	return;
    case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
	if (ctx->fpscr & FPSCR_SZ) {
	    gen_op_fmov_drN_DT0(XREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_add_rN_T1(REG(0));
	    gen_op_stfq_DT0_T1(ctx);
	} else {
	    gen_op_fmov_frN_FT0(FREG(B7_4));
	    gen_op_movl_rN_T1(REG(B11_8));
	    gen_op_add_rN_T1(REG(0));
	    gen_op_stfl_FT0_T1(ctx);
	}
	return;
    case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
    case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
    case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
    case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
    case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
    case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
	if (ctx->fpscr & FPSCR_PR) {
	    if (ctx->opcode & 0x0110)
		break; /* illegal instruction */
	    gen_op_fmov_drN_DT1(DREG(B7_4));
	    gen_op_fmov_drN_DT0(DREG(B11_8));
	}
	else {
	    gen_op_fmov_frN_FT1(FREG(B7_4));
	    gen_op_fmov_frN_FT0(FREG(B11_8));
	}

	switch (ctx->opcode & 0xf00f) {
	case 0xf000:		/* fadd Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT();
	    break;
	case 0xf001:		/* fsub Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT();
	    break;
	case 0xf002:		/* fmul Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT();
	    break;
	case 0xf003:		/* fdiv Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT();
	    break;
	case 0xf004:		/* fcmp/eq Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT();
	    return;
	case 0xf005:		/* fcmp/gt Rm,Rn */
	    ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT();
	    return;
	}

	if (ctx->fpscr & FPSCR_PR) {
	    gen_op_fmov_DT0_drN(DREG(B11_8));
	}
	else {
	    gen_op_fmov_FT0_frN(FREG(B11_8));
	}
	return;
    }

    switch (ctx->opcode & 0xff00) {
    case 0xc900:		/* and #imm,R0 */
	gen_op_and_imm_rN(B7_0, REG(0));
	return;
    case 0xcd00:		/* and.b #imm,@(R0,GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_movl_T0_T1();
	gen_op_ldub_T0_T0(ctx);
	gen_op_and_imm_T0(B7_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0x8b00:		/* bf label */
	CHECK_NOT_DELAY_SLOT
	    gen_conditional_jump(ctx, ctx->pc + 2,
				 ctx->pc + 4 + B7_0s * 2);
	ctx->bstate = BS_BRANCH;
	return;
    case 0x8f00:		/* bf/s label */
	CHECK_NOT_DELAY_SLOT
	    gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
	ctx->flags |= DELAY_SLOT_CONDITIONAL;
	return;
    case 0x8900:		/* bt label */
	CHECK_NOT_DELAY_SLOT
	    gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
				 ctx->pc + 2);
	ctx->bstate = BS_BRANCH;
	return;
    case 0x8d00:		/* bt/s label */
	CHECK_NOT_DELAY_SLOT
	    gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
	ctx->flags |= DELAY_SLOT_CONDITIONAL;
	return;
    case 0x8800:		/* cmp/eq #imm,R0 */
	gen_op_movl_rN_T0(REG(0));
	gen_op_cmp_eq_imm_T0(B7_0s);
	return;
    case 0xc400:		/* mov.b @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_ldb_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc500:		/* mov.w @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0 * 2);
	gen_op_ldw_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc600:		/* mov.l @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0 * 4);
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc000:		/* mov.b R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stb_T0_T1(ctx);
	return;
    case 0xc100:		/* mov.w R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0 * 2);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stw_T0_T1(ctx);
	return;
    case 0xc200:		/* mov.l R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0 * 4);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stl_T0_T1(ctx);
	return;
    case 0x8000:		/* mov.b R0,@(disp,Rn) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_addl_imm_T1(B3_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0x8100:		/* mov.w R0,@(disp,Rn) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_addl_imm_T1(B3_0 * 2);
	gen_op_stw_T0_T1(ctx);
	return;
    case 0x8400:		/* mov.b @(disp,Rn),R0 */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_addl_imm_T0(B3_0);
	gen_op_ldb_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0x8500:		/* mov.w @(disp,Rn),R0 */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_addl_imm_T0(B3_0 * 2);
	gen_op_ldw_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc700:		/* mova @(disp,PC),R0 */
	gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
			   REG(0));
	return;
    case 0xcb00:		/* or #imm,R0 */
	gen_op_or_imm_rN(B7_0, REG(0));
	return;
    case 0xcf00:		/* or.b #imm,@(R0,GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_movl_T0_T1();