📄 ppc_chrp.c
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char partition_name[12] = "wwwwwwwwwwww"; buf[0] = 0x7f; /* free partition magic */ buf[1] = 0; /* checksum */ buf[2] = len >> 8; buf[3] = len; memcpy(buf + 4, partition_name, 12); buf[1] = nvram_chksum(buf, 16);} /* PowerPC CHRP hardware initialisation */static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, int is_heathrow){ CPUState *env; char buf[1024]; SetIRQFunc *set_irq; void *pic; m48t59_t *nvram; int unin_memory; int linux_boot, i; unsigned long bios_offset, vga_bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; ppc_def_t *def; PCIBus *pci_bus; const char *arch_name; int vga_bios_size, bios_size; linux_boot = (kernel_filename != NULL); /* init CPUs */ env = cpu_init(); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); /* Register CPU as a 74x/75x */ /* XXX: CPU model (or PVR) should be provided on command line */ // ppc_find_by_name("750gx", &def); // Linux boot OK // ppc_find_by_name("750fx", &def); // Linux boot OK /* Linux does not boot on 750cxe (and probably other 750cx based) * because it assumes it has 8 IBAT & DBAT pairs as it only have 4. */ // ppc_find_by_name("750cxe", &def); // ppc_find_by_name("750p", &def); // ppc_find_by_name("740p", &def); ppc_find_by_name("750", &def); // ppc_find_by_name("740", &def); // ppc_find_by_name("G3", &def); // ppc_find_by_name("604r", &def); // ppc_find_by_name("604e", &def); // ppc_find_by_name("604", &def); if (def == NULL) { cpu_abort(env, "Unable to find PowerPC CPU definition\n"); } cpu_ppc_register(env, def); /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); env->osi_call = vga_osi_call; /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); /* allocate and load BIOS */ bios_offset = ram_size + vga_ram_size; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); bios_size = load_image(buf, phys_ram_base + bios_offset); if (bios_size < 0 || bios_size > BIOS_SIZE) { fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); exit(1); } bios_size = (bios_size + 0xfff) & ~0xfff; cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM); /* allocate and load VGA BIOS */ vga_bios_offset = bios_offset + bios_size; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8); if (vga_bios_size < 0) { /* if no bios is present, we can still work */ fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf); vga_bios_size = 0; } else { /* set a specific header (XXX: find real Apple format for NDRV drivers) */ phys_ram_base[vga_bios_offset] = 'N'; phys_ram_base[vga_bios_offset + 1] = 'D'; phys_ram_base[vga_bios_offset + 2] = 'R'; phys_ram_base[vga_bios_offset + 3] = 'V'; cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), vga_bios_size); vga_bios_size += 8; } vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); if (kernel_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base); if (initrd_size < 0) { fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } } else { initrd_base = 0; initrd_size = 0; } boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; } if (is_heathrow) { isa_mem_base = 0x80000000; /* Register 2 MB of ISA IO space */ isa_mmio_init(0xfe000000, 0x00200000); /* init basic PC hardware */ pic = heathrow_pic_init(&heathrow_pic_mem_index); set_irq = heathrow_pic_set_irq; pci_bus = pci_grackle_init(0xfec00000, pic); pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size, vga_bios_offset, vga_bios_size); /* XXX: suppress that */ isa_pic = pic_init(pic_irq_request, NULL); /* XXX: use Mac Serial port */ serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); for(i = 0; i < nb_nics; i++) { if (!nd_table[i].model) nd_table[i].model = "ne2k_pci"; pci_nic_init(pci_bus, &nd_table[i], -1); } pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); /* cuda also initialize ADB */ cuda_mem_index = cuda_init(set_irq, pic, 0x12); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); { MacIONVRAMState *nvr; nvr = macio_nvram_init(); pmac_format_nvram_partition(nvr->data, 0x2000); } macio_init(pci_bus, 0x0017); nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59); arch_name = "HEATHROW"; } else { isa_mem_base = 0x80000000; /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); pic = openpic_init(NULL, &openpic_mem_index, 1, &env); set_irq = openpic_set_irq; pci_bus = pci_pmac_init(pic); /* init basic PC hardware */ pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size, vga_bios_offset, vga_bios_size); /* XXX: suppress that */ isa_pic = pic_init(pic_irq_request, NULL); /* XXX: use Mac Serial port */ serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); for(i = 0; i < nb_nics; i++) { pci_ne2000_init(pci_bus, &nd_table[i], -1); } #if 1 ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13); ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14);#else pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);#endif /* cuda also initialize ADB */ cuda_mem_index = cuda_init(set_irq, pic, 0x19); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, 0x0022); nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59); arch_name = "MAC99"; } if (usb_enabled) { usb_ohci_init(pci_bus, 3, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, kernel_base, kernel_size, kernel_cmdline, initrd_base, initrd_size, /* XXX: need an option to load a NVRAM image */ 0, graphic_width, graphic_height, graphic_depth); /* No PCI init: the BIOS will do it */ /* Special port to get debug messages from Open-Firmware */ register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);}static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename){ ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, 0);} static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename){ ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, 1);}QEMUMachine core99_machine = { "mac99", "Mac99 based PowerMAC", ppc_core99_init,};QEMUMachine heathrow_machine = { "g3bw", "Heathrow based PowerMAC", ppc_heathrow_init,};
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