📄 pc.c
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c->init.init_isa (s); } else { if (pci_bus) { c->init.init_pci (pci_bus, s); } } } } } }}#endifstatic void pc_init_ne2k_isa(NICInfo *nd){ static int nb_ne2k = 0; if (nb_ne2k == NE2000_NB_MAX) return; isa_ne2000_init(ne2000_io[nb_ne2k], ne2000_irq[nb_ne2k], nd); nb_ne2k++;}#define NOBIOS 1/* PC hardware initialisation */static void pc_init1(uint64_t ram_size, int vga_ram_size, char *boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, int pci_enabled, const char *direct_pci){#ifndef NOBIOS char buf[1024]; int ret, initrd_size;#endif /* !NOBIOS */ int linux_boot, i;#ifndef NOBIOS unsigned long bios_offset, vga_bios_offset, option_rom_offset; int bios_size, isa_bios_size;#endif /* !NOBIOS */ PCIBus *pci_bus; int piix3_devfn = -1; CPUState *env; NICInfo *nd; int rc; linux_boot = (kernel_filename != NULL); /* init CPUs */ for(i = 0; i < smp_cpus; i++) { env = cpu_init();#ifndef CONFIG_DM if (i != 0) env->hflags |= HF_HALTED_MASK; if (smp_cpus > 1) { /* XXX: enable it in all cases */ env->cpuid_features |= CPUID_APIC; }#endif /* !CONFIG_DM */ register_savevm("cpu", i, 4, cpu_save, cpu_load, env); qemu_register_reset(main_cpu_reset, env);#ifndef CONFIG_DM if (pci_enabled) { apic_init(env); }#endif /* !CONFIG_DM */ } /* allocate RAM */#ifndef CONFIG_DM /* HVM domain owns memory */ cpu_register_physical_memory(0, ram_size, 0);#endif#ifndef NOBIOS /* BIOS load */ bios_offset = ram_size + vga_ram_size; vga_bios_offset = bios_offset + 256 * 1024; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); bios_size = get_image_size(buf); if (bios_size <= 0 || (bios_size % 65536) != 0 || bios_size > (256 * 1024)) { goto bios_error; } ret = load_image(buf, phys_ram_base + bios_offset); if (ret != bios_size) { bios_error: fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf); exit(1); } /* VGA BIOS load */ if (cirrus_vga_enabled) { snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); } else { snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); } ret = load_image(buf, phys_ram_base + vga_bios_offset);#endif /* !NOBIOS */ /* setup basic memory access */#ifndef CONFIG_DM /* HVM domain owns memory */ cpu_register_physical_memory(0xc0000, 0x10000, vga_bios_offset | IO_MEM_ROM);#endif#ifndef NOBIOS /* map the last 128KB of the BIOS in ISA space */ isa_bios_size = bios_size; if (isa_bios_size > (128 * 1024)) isa_bios_size = 128 * 1024; cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size, IO_MEM_UNASSIGNED); cpu_register_physical_memory(0x100000 - isa_bios_size, isa_bios_size, (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); option_rom_offset = 0; for (i = 0; i < nb_option_roms; i++) { int offset = bios_offset + bios_size + option_rom_offset; int size; size = load_image(option_rom[i], phys_ram_base + offset); if ((size + option_rom_offset) > 0x10000) { fprintf(stderr, "Too many option ROMS\n"); exit(1); } cpu_register_physical_memory(0xd0000 + option_rom_offset, size, offset | IO_MEM_ROM); option_rom_offset += size + 2047; option_rom_offset -= (option_rom_offset % 2048); } /* map all the bios at the top of memory */ cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM);#endif bochs_bios_init(); if (linux_boot) load_linux(kernel_filename, initrd_filename, kernel_cmdline); if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state); piix3_devfn = piix3_init(pci_bus, -1); } else { pci_bus = NULL; } /* init basic PC hardware */ register_ioport_write(0x80, 1, 1, ioport80_write, NULL); register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); if (cirrus_vga_enabled) { if (pci_enabled) { pci_cirrus_vga_init(pci_bus, ds, NULL, ram_size, vga_ram_size); } else { isa_cirrus_vga_init(ds, NULL, ram_size, vga_ram_size); } } else { if (pci_enabled) { pci_vga_init(pci_bus, ds, NULL, ram_size, vga_ram_size, 0, 0); } else { isa_vga_init(ds, NULL, ram_size, vga_ram_size); } }#ifdef CONFIG_PASSTHROUGH /* Pass-through Initialization * init libpci even direct_pci is null, as can hotplug a dev runtime */ if ( pci_enabled ) { rc = pt_init(pci_bus, direct_pci); if ( rc < 0 ) { fprintf(logfile, "Error: Initialization failed for pass-through devices\n"); exit(1); } }#endif rtc_state = rtc_init(0x70, 8); register_ioport_read(0x92, 1, 1, ioport92_read, NULL); register_ioport_write(0x92, 1, 1, ioport92_write, NULL);#ifndef CONFIG_DM if (pci_enabled) { ioapic = ioapic_init(); }#endif /* !CONFIG_DM */ isa_pic = pic_init(pic_irq_request, first_cpu);#ifndef CONFIG_DM pit = pit_init(0x40, 0); pcspk_init(pit);#endif /* !CONFIG_DM */#ifndef CONFIG_DM if (pci_enabled) { pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); }#endif /* !CONFIG_DM */ if (pci_enabled) pci_xen_platform_init(pci_bus); for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { serial_init(&pic_set_irq_new, isa_pic, serial_io[i], serial_irq[i], serial_hds[i]); } } for(i = 0; i < MAX_PARALLEL_PORTS; i++) { if (parallel_hds[i]) { parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]); } } for(i = 0; i < nb_nics; i++) { nd = &nd_table[i]; if (!nd->model) { if (pci_enabled) { nd->model = "ne2k_pci"; } else { nd->model = "ne2k_isa"; } } if (strcmp(nd->model, "ne2k_isa") == 0) { pc_init_ne2k_isa(nd); } else if (pci_enabled) { pci_nic_init(pci_bus, nd, -1); } else { fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); exit(1); } } if (pci_enabled) { pci_piix3_ide_init(pci_bus, bs_table, piix3_devfn + 1); } else { for(i = 0; i < 2; i++) { isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], bs_table[2 * i], bs_table[2 * i + 1]); } }#ifdef HAS_TPM if (has_tpm_device()) tpm_tis_init(&pic_set_irq_new, isa_pic, 11);#endif kbd_init(); DMA_init(0);#ifdef HAS_AUDIO audio_init(pci_enabled ? pci_bus : NULL);#endif floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table); cmos_init(ram_size, boot_device, bs_table); /* using PIIX4 acpi model */ if (pci_enabled && acpi_enabled) pci_piix4_acpi_init(pci_bus, piix3_devfn + 2); if (pci_enabled && usb_enabled) { usb_uhci_init(pci_bus, piix3_devfn + (acpi_enabled ? 3 : 2)); }#ifndef CONFIG_DM if (pci_enabled && acpi_enabled) { uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ piix4_pm_init(pci_bus, piix3_devfn + 3); for (i = 0; i < 8; i++) { SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i, eeprom_buf + (i * 256)); piix4_smbus_register_device(eeprom, 0x50 + i); } } if (i440fx_state) { i440fx_init_memory_mappings(i440fx_state); }#if 0 /* ??? Need to figure out some way for the user to specify SCSI devices. */ if (pci_enabled) { void *scsi; BlockDriverState *bdrv; scsi = lsi_scsi_init(pci_bus, -1); bdrv = bdrv_new("scsidisk"); bdrv_open(bdrv, "scsi_disk.img", 0); lsi_scsi_attach(scsi, bdrv, -1); bdrv = bdrv_new("scsicd"); bdrv_open(bdrv, "scsi_cd.iso", 0); bdrv_set_type_hint(bdrv, BDRV_TYPE_CDROM); lsi_scsi_attach(scsi, bdrv, -1); }#endif#else if (pci_enabled) { void *scsi = NULL; for (i = 0; i < MAX_SCSI_DISKS ; i++) { if (!bs_table[i + MAX_DISKS]) continue; if (!scsi) scsi = lsi_scsi_init(pci_bus, -1); lsi_scsi_attach(scsi, bs_table[i + MAX_DISKS], -1); } }#endif /* !CONFIG_DM */ if (pci_enabled) { PCI_EMULATION_INFO *p; for (p = PciEmulationInfoHead; p != NULL; p = p->next) { pci_emulation_init(pci_bus, p); } }}static void pc_init_pci(uint64_t ram_size, int vga_ram_size, char *boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *direct_pci){ pc_init1(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, 1, direct_pci);}static void pc_init_isa(uint64_t ram_size, int vga_ram_size, char *boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *unused){ pc_init1(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, 0, NULL);}/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) BIOS will read it and start S3 resume at POST Entry*/void cmos_set_s3_resume(void){ if (rtc_state) rtc_set_memory(rtc_state, 0xF, 0xFE);}QEMUMachine pc_machine = { "pc", "Standard PC", pc_init_pci,};QEMUMachine isapc_machine = { "isapc", "ISA-only PC", pc_init_isa,};
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