asyn_comp.v

来自「verilog编写的异步fifo源代码」· Verilog 代码 · 共 28 行

//异步比较模块
module asyn_comp
#(
	parameter
	ADDR_WIDTH = 4
)
(
	output wire asyn_empty,
	output wire asyn_full,
	input wire rst_n,
	input wire [ADDR_WIDTH-1 : 0] w_ptr,
	input wire [ADDR_WIDTH-1 : 0] r_ptr
);

wire dirset;
wire dirclr;

assign dirset = (w_ptr[ADDR_WIDTH-1] ^ r_ptr[ADDR_WIDTH-2]) & (~(w_ptr[ADDR_WIDTH-2] ^ r_ptr[ADDR_WIDTH-1]));
assign dirclr = (~(w_ptr[ADDR_WIDTH-1] ^ r_ptr[ADDR_WIDTH-2])) & (w_ptr[ADDR_WIDTH-2] ^ r_ptr[ADDR_WIDTH-1]);


wire direction;
assign direction = ~((~(dirset | direction)) | dirclr | (~rst_n));

assign asyn_empty = ~((w_ptr == r_ptr) && (direction == 1'b0));
assign asyn_full = ~((w_ptr == r_ptr) && (direction == 1'b1));

endmodule