dp_ram.v

verilog编写的异步fifo源代码

module dp_ram
#(
	parameter
	DATA_WIDTH = 16,
	ADDR_WIDTH = 4,
	DEPTH = 2**ADDR_WIDTH
)
(
	output wire [DATA_WIDTH-1 : 0] rdata,
	input wire [DATA_WIDTH-1 : 0] wdata,
	input wire [ADDR_WIDTH-1 : 0] waddr,
	input wire [ADDR_WIDTH-1 : 0] raddr,
	input wire w_clk
);

reg [DATA_WIDTH-1 : 0] mem [DEPTH-1 : 0];

always @ (posedge w_clk)
	mem[waddr] <= wdata;

assign rdata = mem[raddr];

endmodule