mx21_cspi.h

BGW211针对freescale的MX21的无线WIFI驱动（WINCE5.0）

//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// Freescale Semiconductor, Inc.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2005, MOTOROLA, INC. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// MOTOROLA, INC.
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//  Header:  mx21_cspi.h
//
//  Provides definitions for CSPI module on i.MX21.
//
//------------------------------------------------------------------------------

#ifndef __MX21_CSPI_H
#define __MX21_CSPI_H

#if __cplusplus
extern "C" {
#endif


//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
#define CSPI_FIFO_SLOT_MAX      8

//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
    REG32 RXDATA;
    REG32 TXDATA;
    REG32 CONTROLREG;
    REG32 INT;
    REG32 TEST;
    REG32 PERIOD;
    REG32 DMA;
    REG32 RESET;
} CSP_CSPI_REGS, *PCSP_CSPI_REGS;


//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
#define CSPI_RXDATA_OFFSET              0x0000
#define CSPI_TXDATA_OFFSET              0x0004
#define CSPI_CONTROLREG_OFFSET          0x0008
#define CSPI_INT_OFFSET                 0x000C
#define CSPI_TEST_OFFSET                0x0010
#define CSPI_PERIOD_OFFSET              0x0014
#define CSPI_DMA_OFFSET                 0x0018
#define CSPI_RESET_OFFSET               0x001C

//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define CSPI_RXDATA_LSH                 0

#define CSPI_TXDATA_LSH                 0

#define CSPI_CONTROLREG_BITCOUNT_LSH    0
#define CSPI_CONTROLREG_POL_LSH         5
#define CSPI_CONTROLREG_PHA_LSH         6
#define CSPI_CONTROLREG_SSCTL_LSH       7
#define CSPI_CONTROLREG_SSPOL_LSH       8
#define CSPI_CONTROLREG_XCH_LSH         9
#define CSPI_CONTROLREG_SPIEN_LSH       10
#define CSPI_CONTROLREG_MODE_LSH        11
#define CSPI_CONTROLREG_DRCTL_LSH       12
#define CSPI_CONTROLREG_DATARATE_LSH    14
#define CSPI_CONTROLREG_CS_LSH          19
#define CSPI_CONTROLREG_SWAP_LSH        21
#define CSPI_CONTROLREG_SDHC_SPIEN_LSH  22
#define CSPI_CONTROLREG_BURST_LSH       23

#define CSPI_INT_TE_LSH                 0
#define CSPI_INT_TH_LSH                 1
#define CSPI_INT_TF_LSH                 2
#define CSPI_INT_TSHFE_LSH              3
#define CSPI_INT_RR_LSH                 4
#define CSPI_INT_RH_LSH                 5
#define CSPI_INT_RF_LSH                 6
#define CSPI_INT_RO_LSH                 7
#define CSPI_INT_BO_LSH                 8
#define CSPI_INT_TEEN_LSH               9
#define CSPI_INT_THEN_LSH               10
#define CSPI_INT_TFEN_LSH               11
#define CSPI_INT_TSHFEEN_LSH            12
#define CSPI_INT_RREN_LSH               13
#define CSPI_INT_RHEN_LSH               14
#define CSPI_INT_RFEN_LSH               15
#define CSPI_INT_ROEN_LSH               16
#define CSPI_INT_BOEN_LSH               17

#define CSPI_TEST_TXCNT_LSH             0
#define CSPI_TEST_RXCNT_LSH             4
#define CSPI_TEST_SSSTATUS_LSH          8
#define CSPI_TEST_SS_ASSERT_LSH         12
#define CSPI_TEST_INIT_LSH              13
#define CSPI_TEST_LBC_LSH               14

#define CSPI_PERIOD_WAIT_LSH            0
#define CSPI_PERIOD_CSRC_LSH            15

#define CSPI_DMA_RHDMA_LSH              4
#define CSPI_DMA_RFDMA_LSH              5
#define CSPI_DMA_TEDMA_LSH              6
#define CSPI_DMA_THDMA_LSH              7
#define CSPI_DMA_RHDEN_LSH              12
#define CSPI_DMA_RFDEN_LSH              13
#define CSPI_DMA_TEDEN_LSH              14
#define CSPI_DMA_THDEN_LSH              15

#define CSPI_RESET_START_LSH            0

//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define CSPI_RXDATA_WID                 32

#define CSPI_TXDATA_WID                 32

#define CSPI_CONTROLREG_BITCOUNT_WID    5
#define CSPI_CONTROLREG_POL_WID         1
#define CSPI_CONTROLREG_PHA_WID         1
#define CSPI_CONTROLREG_SSCTL_WID       1
#define CSPI_CONTROLREG_SSPOL_WID       1
#define CSPI_CONTROLREG_XCH_WID         1
#define CSPI_CONTROLREG_SPIEN_WID       1
#define CSPI_CONTROLREG_MODE_WID        1
#define CSPI_CONTROLREG_DRCTL_WID       2
#define CSPI_CONTROLREG_DATARATE_WID    5
#define CSPI_CONTROLREG_CS_WID          2
#define CSPI_CONTROLREG_SWAP_WID        1
#define CSPI_CONTROLREG_SDHC_SPIEN_WID  1
#define CSPI_CONTROLREG_BURST_WID       1

#define CSPI_INT_TE_WID                 1
#define CSPI_INT_TH_WID                 1
#define CSPI_INT_TF_WID                 1
#define CSPI_INT_TSHFE_WID              1
#define CSPI_INT_RR_WID                 1
#define CSPI_INT_RH_WID                 1
#define CSPI_INT_RF_WID                 1
#define CSPI_INT_RO_WID                 1
#define CSPI_INT_BO_WID                 1
#define CSPI_INT_TEEN_WID               1
#define CSPI_INT_THEN_WID               1
#define CSPI_INT_TFEN_WID               1
#define CSPI_INT_TSHFEEN_WID            1
#define CSPI_INT_RREN_WID               1
#define CSPI_INT_RHEN_WID               1
#define CSPI_INT_RFEN_WID               1
#define CSPI_INT_ROEN_WID               1
#define CSPI_INT_BOEN_WID               1

#define CSPI_TEST_TXCNT_WID             4
#define CSPI_TEST_RXCNT_WID             4
#define CSPI_TEST_SSSTATUS_WID          4
#define CSPI_TEST_SS_ASSERT_WID         2
#define CSPI_TEST_INIT_WID              1
#define CSPI_TEST_LBC_WID               1