bsp_cfg.h

BGW211针对freescale的MX21的无线WIFI驱动（WINCE5.0）

//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  FREESCALE SEMICONDUCTOR, INC.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2005, MOTOROLA, INC. All Rights Reserved
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  MOTOROLA, INC.
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for MX21 reference ADS.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootloader/KITL
//
#define BSP_DEVICE_PREFIX       "MX21"              // Device name prefix

//------------------------------------------------------------------------------
// Clock Configuration Settings
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// BSP_PLL_SRC_FREQ specifies frequency of osc crystal used for the MX21.
// It must be one of the following:
//  PLL_SRC_FREQ_32768KHZ
//  PLL_SRC_FREQ_32000KHZ
//  PLL_SRC_FREQ_26MHZ
//
// BSP_REF_32KHZ_FREQ specifies frequency of 32kHz ref clock used for the MX21.
// It must be one of the following:
//  PLL_SRC_FREQ_32768KHZ
//  PLL_SRC_FREQ_32000KHZ
//------------------------------------------------------------------------------
#define PLL_SRC_FREQ_32768KHZ           32768
#define PLL_SRC_FREQ_32000KHZ           32000		// not support
#define PLL_SRC_FREQ_26MHZ              26000000	// not support

#define BSP_PLL_SRC_FREQ                PLL_SRC_FREQ_32768KHZ
#define BSP_REF_32KHZ_FREQ              PLL_SRC_FREQ_32768KHZ

//------------------------------------------------------------------------------
// BSP_FCLK_HCLK_SETTING specifies FCLK/HCLK combination used for the MX21.
// It must be one of the following:
//   FCLK_HCLK_350_116
//   FCLK_HCLK_266_133
//   FCLK_HCLK_266_88 
//   FCLK_HCLK_266_66 
//   FCLK_HCLK_133_66 
//   FCLK_HCLK_66_66  
//   FCLK_HCLK_66_33  
//------------------------------------------------------------------------------
#define FCLK_HCLK_66_33         0
#define FCLK_HCLK_66_66         1
#define FCLK_HCLK_133_66        2
#define FCLK_HCLK_266_66        3               
#define FCLK_HCLK_266_88        4
#define FCLK_HCLK_266_133       5
#define FCLK_HCLK_350_116       6
// Add other combinations here.

#if (MX21_FCLK_MHZ == 266)
#ifndef HCLK_88MHZ_PCMCIA
#define BSP_FCLK_HCLK_SETTING           FCLK_HCLK_266_133
#else
// PCMCIA has to work under 88 MHz HCLK
#define BSP_FCLK_HCLK_SETTING           FCLK_HCLK_266_88
#endif
#elif (MX21_FCLK_MHZ == 350)
#define BSP_FCLK_HCLK_SETTING           FCLK_HCLK_350_116
#else
#error "Invalid MX21_FCLK_MHZ value!"
#endif

//------------------------------------------------------------------------------
// BSP_NOR_BURST_MODE specifies whether NOR flash on MX21 ADS is used in
// burst mode.
// It must be one of the following:
//  BSP_NOR_BURST_NOT_SUPPORTED
//  BSP_NOR_BURST_SUPPORTED
//------------------------------------------------------------------------------
#define BSP_NOR_BURST_MODE_DISABLED         0
#define BSP_NOR_BURST_MODE_ENABLED          1

#if (BSP_FCLK_HCLK_SETTING == FCLK_HCLK_350_116 || BSP_FCLK_HCLK_SETTING == FCLK_HCLK_266_133 || BSP_FCLK_HCLK_SETTING == FCLK_HCLK_266_88)
#define BSP_NOR_BURST_MODE              BSP_NOR_BURST_MODE_ENABLED
#else
#define BSP_NOR_BURST_MODE              BSP_NOR_BURST_MODE_DISABLED
#endif

#if (BSP_NOR_BURST_MODE == BSP_NOR_BURST_MODE_ENABLED)
//------------------------------------------------------------------------------
// BSP_NOR_BURST_CLK_FREQ specifies what burst clock is used with the NOR flash on 
// MX21 ADS.
// It must be one of the following:
//  BSP_NOR_BURST_CLK_44MHZ
//  BSP_NOR_BURST_CLK_66MHZ (Currently only suppported for 266/133 FCLK/HCLK)
//------------------------------------------------------------------------------
#define BSP_NOR_BURST_CLK_44MHZ         0
#define BSP_NOR_BURST_CLK_66MHZ         1

#define BSP_NOR_BURST_CLK_FREQ          BSP_NOR_BURST_CLK_44MHZ
#endif

//------------------------------------------------------------------------------
// BSP_KPP_ROW_INUSE specifies what keypad rows are used on MX21 ADS.
// BSP_KPP_COL_INUSE specifies what keypad rows are used on MX21 ADS.
//------------------------------------------------------------------------------
#define BSP_KPP_ROW_INUSE               6    // Row1-Row5 
#define BSP_KPP_COL_INUSE               6    // Col1-Col5

//------------------------------------------------------------------------------
// Interrupt Requests
//------------------------------------------------------------------------------
#define BSP_PEN_IRQ         IRQ_GPIO_PE_10      // Touch pen IRQ tied to GPIO PE10
#define BSP_CS8900_IRQ      IRQ_GPIO_PE_11      // CS8900 IRQ tied to GPIO PE11
#define BSP_SDHC_DET_IRQ    IRQ_GPIO_PD_25      // SDHC pen IRQ tied to GPIO PD25
#define BSP_WAVEDEV_TX_IRQ  IRQ_DMACH15         // TX uses CH15 for DMA
#define BSP_WAVEDEV_RX_IRQ  IRQ_DMACH14         // RX uses CH14 for DMA
#define BSP_CSPI2_TX_IRQ    IRQ_DMACH8          // TX uses CH8 for DMA
#define BSP_CSPI2_RX_IRQ    IRQ_DMACH9          // RX uses CH9 for DMA
#define BSP_BGW211_EXT_IRQ  IRQ_GPIO_PD_20      // BGW211 IRQ tied to GPIO PD20



//------------------------------------------------------------------------------
// Debug OUTPUT
// DEBUG_PORT specifies which UART we use for debug serial port. It must be one
// of the following :
//     DBG_SERIAL_PORT_UART1
//     DBG_SERIAL_PORT_ST16C2552_PORTA
//     DBG_SERIAL_PORT_ST16C2552_PORTB
//------------------------------------------------------------------------------
#define DBG_SERIAL_UART1           0
#define DBG_SERIAL_ST16C2552_PORTA  4
#define DBG_SERIAL_ST16C2552_PORTB  5

#if SERIALDBG_INT
#define BSP_DBG_SERIAL_PORT       DBG_SERIAL_UART1
#else
#define BSP_DBG_SERIAL_PORT       DBG_SERIAL_ST16C2552_PORTA
#endif

//------------------------------------------------------------------------------
// BSP_BOOTCFG_STORAGE specifies what storage is used for storing boot 
// configuration data.
// It must be one of the following :
//     BOOTCFG_STORAGE_NAND
//     BOOTCFG_STORAGE_EEPROM
//-----------------------------------------------------------------------------
#define BOOTCFG_STORAGE_NAND        0
#define BOOTCFG_STORAGE_EEPROM      1

#define BSP_BOOTCFG_STORAGE         BOOTCFG_STORAGE_EEPROM
//#define BOOTCFG_STORAGE             BOOTCFG_STORAGE_NAND

//------------------------------------------------------------------------------
// BSP_DISPLAY_CONTROLLER specifies which display controller is used. 
// It must be one of the following :
//     DISPLAY_CONTROLLER_LCDC
//     DISPLAY_CONTROLLER_SLCDC
//     DISPLAY_CONTROLLER_BMI
//
//-----------------------------------------------------------------------------
#define DISPLAY_CONTROLLER_LCDC     0
#define DISPLAY_CONTROLLER_SLCDC    1
#define DISPLAY_CONTROLLER_BMI      2

#ifndef BSP_SLCDC
#define BSP_DISPLAY_CONTROLLER      DISPLAY_CONTROLLER_LCDC 
#else
#define BSP_DISPLAY_CONTROLLER      DISPLAY_CONTROLLER_SLCDC
#endif

//------------------------------------------------------------------------------
// BSP_DISPLAY_PANEL specifies which screen panel is used. 
// It must be one of the following :
//     DISPLAY_PANEL_QVGA (Sharp panel)
//     DISPLAY_PANEL_VGA (NEC panel)
//     DISPLAY_PANEL_SMARTPHONE (SLCDC panel)
// BSP_DISPLAY_SCREEN_WIDTH specifies lcd display width. 
// BSP_DISPLAY_SCREEN_HEIGHT specifies lcd display height.
// BSP_PIXEL_CLOCK_FREQ specifies the max pixel clock freq supported by the 
// MX21 LCD panel.
// 
//------------------------------------------------------------------------------
#define DISPLAY_PANEL_QVGA_PORTRAIT          0 // Using Sharp LQ035Q7DB02 QVGA TFT-LCD 
#define DISPLAY_PANEL_VGA_LANDSCAPE          1 // Using NEC NL6448BC33-46 VGA TFF-LCD
#define DISPLAY_PANEL_SMARTPHONE_PORTRAIT    2 // Using Epson  

// Display panel support selection
#define BSP_DISPLAY_PANEL           DISPLAY_PANEL_QVGA_PORTRAIT

#if (BSP_DISPLAY_PANEL == DISPLAY_PANEL_QVGA_PORTRAIT)
#define BSP_DISPLAY_SCREEN_WIDTH    240
#define BSP_DISPLAY_SCREEN_HEIGHT   320
#define BSP_PIXEL_CLOCK_FREQ        6800000 // 4.5-6.8MHz
#elif (BSP_DISPLAY_PANEL == DISPLAY_PANEL_VGA_LANDSCAPE)
#define BSP_DISPLAY_SCREEN_WIDTH    640
#define BSP_DISPLAY_SCREEN_HEIGHT   240
#define BSP_PIXEL_CLOCK_FREQ        25200000 // 25.2Mhz
#elif (BSP_DISPLAY_PANEL == DISPLAY_PANEL_SMARTPHONE_PORTRAIT)
#define BSP_DISPLAY_SCREEN_WIDTH    176
#define BSP_DISPLAY_SCREEN_HEIGHT   220
// TODO: BSP_PIXEL_CLOCK_FREQ
#else
#error "Unknown display panel selection!"
#endif

//------------------------------------------------------------------------------
// BSP_DISPLAY_BPP specifies the desired display bpp mode.
// Notes:
// The display will be set up to use this mode on boot but the display driver
// may change to other modes as specified in registry if supported. 
// It must be one of the following :
//     BSP_DISPLAY_1BPP 
//     BSP_DISPLAY_2BPP 
//     BSP_DISPLAY_4BPP 
//     BSP_DISPLAY_8BPP 
//     BSP_DISPLAY_12BPP 
//     BSP_DISPLAY_16BPP 
//     BSP_DISPLAY_18BPP 
// 
//------------------------------------------------------------------------------
#define BSP_DISPLAY_1BPP        1 
#define BSP_DISPLAY_2BPP        2
#define BSP_DISPLAY_4BPP        4
#define BSP_DISPLAY_8BPP        8
#define BSP_DISPLAY_12BPP       12
#define BSP_DISPLAY_16BPP       16
#define BSP_DISPLAY_18BPP       18

#define BSP_DISPLAY_BPP         BSP_DISPLAY_16BPP

// BSP_SPLASH_SCREEN_BACKGROUND specifies color to fill background with for 
// splashscreen display on boot.
#define BSP_SPLASH_SCREEN_BACKGROUND 0xFF

//------------------------------------------------------------------------------
// BSP_FREE_TIMER specifies the free timer that can be used.
// BSP_TOUCH_TIMER specifies the dedicated timer used by touch driver.
// Notes:
// It must be one of the following :
//     BSP_TIMER_GPT1   (System timer)
//     BSP_TIMER_GPT2   (touch timer)
//     BSP_TIMER_GPT3   (Profiling or free timer)
// 
//------------------------------------------------------------------------------
#define BSP_TIMER_GPT1      0
#define BSP_TIMER_GPT2      1
#define BSP_TIMER_GPT3      2

#ifdef IMGPROFILER
#pragma message("WARNING! GPT3 is already used for profiling!")
#endif

#define BSP_FREE_TIMER          BSP_TIMER_GPT3
#define BSP_TOUCH_TIMER         BSP_TIMER_GPT2

//------------------------------------------------------------------------------
// BSP_DMA_CH_AUDIO_TX specifies the dmac channel used for audio tx.
// BSP_DMA_CH_AUDIO_RX specifies the dmac channel used for audio rx.
// BSP_DMA_CH_SDHC_TX specifies the dmac channel used for SDHC tx.
// BSP_DMA_CH_SDHC_RX specifies the dmac channel used for SDHC tx.
// BSP_DMA_CH_FIRI_TX specifies the dmac channel used for FIRI tx.
// BSP_DMA_CH_FIRI_RX specifies the dmac channel used for FIRI rx.
// Notes:
// must be one of the following :
//     0      (lowest priority)
//      ....
//     15     (highest priority)
// 
//------------------------------------------------------------------------------

#define BSP_DMAC_CH_AUDIO_TX        15         
#define BSP_DMAC_CH_AUDIO_RX        14
#define BSP_DMAC_CH_SDHC_TX         13
#define BSP_DMAC_CH_SDHC_RX         12
#define BSP_DMAC_CH_FIRI_TX         11
#define BSP_DMAC_CH_FIRI_RX         10

#define BSP_DMAC_AUDIO_BUFF_SIZE    (0x00002000)         
#define BSP_DMAC_SDHC_BUFF_SIZE     (0x00020000)         
#define BSP_DMAC_FIRI_BUFF_SIZE     (0x0000F000)         

//------------------------------------------------------------------------------

#endif