bsp_cfg.h

SMDK2440A_CE5.0_20060703(官方终结版).rar 从此告别“恶意篡改”的开发板提供商的非规范BSP

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for SMDK2440A board.
//
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX       "SMDK2440"        // Device name prefix
//------------------------------------------------------------------------------
// Board clock
//------------------------------------------------------------------------------

//#define S3C2440A_FCLK           296352000           // 296.352MHz
#define S3C2440A_FCLK           399651840           // 399.65MHz
#define S3C2440A_HCLK           (S3C2440A_FCLK/3)   // divisor 6
#define S3C2440A_PCLK           (S3C2440A_FCLK/6)   // divisor 6

//------------------------------------------------------------------------------
// Debug UART1
//------------------------------------------------------------------------------

#define BSP_UART1_ULCON         0x03                // 8 bits, 1 stop, no parity
#define BSP_UART1_UCON          0x0005              // pool mode, PCLK for UART
#define BSP_UART1_UFCON         0x00                // disable FIFO
#define BSP_UART1_UMCON         0x00                // disable auto flow control
#define BSP_UART1_UBRDIV        (S3C2440A_PCLK/(115200*16) - 1)

//------------------------------------------------------------------------------
// Static SYSINTR Mapping for driver.
#define SYSINTR_OHCI            (SYSINTR_FIRMWARE+1)

// -----------------------------------------------------------------------------
// define For DVS
#define V080	0
#define V090	1
#define V095	2
#define V0975	3
#define V100	4
#define V105	5
#define V110	6
#define V115	7
#define V120	8
#define V125	9
#define V130	10
#define V135	11
#define V140	12
#define V145	13
#define V150	14

#define DVS_METHOD	1  //1:DVS_ON with VSYNC, 2:DVS_ON in idle mode(not change HCLK), 3:mixed
#define USESWPWSAVING	1
#define MVAL_USED		0
#define HIGHVOLTAGE		V130
#define LOWVOLTAGE		V100
#define VOLTAGEDELAY	16000

#define Eval_Probe		1

#define DVSON		0x1
#define HCLKHALF	0x2
#define ACTIVE		0x4
#define DeepIdle	(DVSON|HCLKHALF)
#define NIdle		(DVSON)
#define LazyActive	(ACTIVE|DVSON|HCLKHALF)
#define SlowActive	(ACTIVE|DVSON)
#define Active		(ACTIVE)
//------------------------------------------------------------

#endif