📄 cstartup.lst
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************************
218 00000000 ;- SOFTWARE API DEFINITION FOR Clock Gener
ator Controler
219 00000000 ;- *****************************************************
************************
220 00000000 ^ 0 ;- AT91S_CKGR
221 00000000 00000000
CKGR_MOR
# 4 ;- Main Oscillator
Register
222 00000000 00000004
CKGR_MCFR
# 4 ;- Main Clock Freq
uency Register
223 00000000 00000008 # 4 ;- Reserved
224 00000000 0000000C
CKGR_PLLR
# 4 ;- PLL Register
225 00000000 ;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillato
r Register --------
226 00000000 00000001
AT91C_CKGR_MOSCEN
EQU (0x1:SHL:0) ;- (CKGR) Main Osci
llator Enable
227 00000000 00000002
AT91C_CKGR_OSCBYPASS
EQU (0x1:SHL:1) ;- (CKGR) Main Osci
llator Bypass
228 00000000 0000FF00
AT91C_CKGR_OSCOUNT
ARM Macro Assembler Page 13
EQU (0xFF:SHL:8) ;- (CKGR) Main Osc
illator Start-up Ti
me
229 00000000 ;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Fr
equency Register --------
230 00000000 0000FFFF
AT91C_CKGR_MAINF
EQU (0xFFFF:SHL:0) ;- (CKGR) Main C
lock Frequency
231 00000000 00010000
AT91C_CKGR_MAINRDY
EQU (0x1:SHL:16) ;- (CKGR) Main Clo
ck Ready
232 00000000 ;- -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Registe
r --------
233 00000000 000000FF
AT91C_CKGR_DIV
EQU (0xFF:SHL:0) ;- (CKGR) Divider
Selected
234 00000000 00000000
AT91C_CKGR_DIV_0
EQU (0x0) ;- (CKGR) Divider o
utput is 0
235 00000000 00000001
AT91C_CKGR_DIV_BYPASS
EQU (0x1) ;- (CKGR) Divider i
s bypassed
236 00000000 00003F00
AT91C_CKGR_PLLCOUNT
EQU (0x3F:SHL:8) ;- (CKGR) PLL Coun
ter
237 00000000 0000C000
AT91C_CKGR_OUT
EQU (0x3:SHL:14) ;- (CKGR) PLL Outp
ut Frequency Range
238 00000000 00000000
AT91C_CKGR_OUT_0
EQU (0x0:SHL:14) ;- (CKGR) Please r
efer to the PLL dat
asheet
239 00000000 00004000
AT91C_CKGR_OUT_1
EQU (0x1:SHL:14) ;- (CKGR) Please r
efer to the PLL dat
asheet
240 00000000 00008000
AT91C_CKGR_OUT_2
EQU (0x2:SHL:14) ;- (CKGR) Please r
efer to the PLL dat
asheet
241 00000000 0000C000
AT91C_CKGR_OUT_3
EQU (0x3:SHL:14) ;- (CKGR) Please r
efer to the PLL dat
asheet
242 00000000 07FF0000
AT91C_CKGR_MUL
EQU (0x7FF:SHL:16) ;- (CKGR) PLL Mu
ltiplier
ARM Macro Assembler Page 14
243 00000000 30000000
AT91C_CKGR_USBDIV
EQU (0x3:SHL:28) ;- (CKGR) Divider
for USB Clocks
244 00000000 00000000
AT91C_CKGR_USBDIV_0
EQU (0x0:SHL:28) ;- (CKGR) Divider
output is PLL clock
output
245 00000000 10000000
AT91C_CKGR_USBDIV_1
EQU (0x1:SHL:28) ;- (CKGR) Divider
output is PLL clock
output divided by
2
246 00000000 20000000
AT91C_CKGR_USBDIV_2
EQU (0x2:SHL:28) ;- (CKGR) Divider
output is PLL clock
output divided by
4
247 00000000
248 00000000 ;- *****************************************************
************************
249 00000000 ;- SOFTWARE API DEFINITION FOR Power Manag
ement Controler
250 00000000 ;- *****************************************************
************************
251 00000000 ^ 0 ;- AT91S_PMC
252 00000000 00000000
PMC_SCER
# 4 ;- System Clock Ena
ble Register
253 00000000 00000004
PMC_SCDR
# 4 ;- System Clock Dis
able Register
254 00000000 00000008
PMC_SCSR
# 4 ;- System Clock Sta
tus Register
255 00000000 0000000C # 4 ;- Reserved
256 00000000 00000010
PMC_PCER
# 4 ;- Peripheral Clock
Enable Register
257 00000000 00000014
PMC_PCDR
# 4 ;- Peripheral Clock
Disable Register
258 00000000 00000018
PMC_PCSR
# 4 ;- Peripheral Clock
Status Register
259 00000000 0000001C # 4 ;- Reserved
260 00000000 00000020
PMC_MOR # 4 ;- Main Oscillator
Register
261 00000000 00000024
ARM Macro Assembler Page 15
PMC_MCFR
# 4 ;- Main Clock Freq
uency Register
262 00000000 00000028 # 4 ;- Reserved
263 00000000 0000002C
PMC_PLLR
# 4 ;- PLL Register
264 00000000 00000030
PMC_MCKR
# 4 ;- Master Clock Reg
ister
265 00000000 00000034 # 12 ;- Reserved
266 00000000 00000040
PMC_PCKR
# 12 ;- Programmable Clo
ck Register
267 00000000 0000004C # 20 ;- Reserved
268 00000000 00000060
PMC_IER # 4 ;- Interrupt Enable
Register
269 00000000 00000064
PMC_IDR # 4 ;- Interrupt Disabl
e Register
270 00000000 00000068
PMC_SR # 4 ;- Status Register
271 00000000 0000006C
PMC_IMR # 4 ;- Interrupt Mask R
egister
272 00000000 ;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock En
able Register --------
273 00000000 00000001
AT91C_PMC_PCK
EQU (0x1:SHL:0) ;- (PMC) Processor
Clock
274 00000000 00000080
AT91C_PMC_UDP
EQU (0x1:SHL:7) ;- (PMC) USB Device
Port Clock
275 00000000 00000100
AT91C_PMC_PCK0
EQU (0x1:SHL:8) ;- (PMC) Programmab
le Clock Output
276 00000000 00000200
AT91C_PMC_PCK1
EQU (0x1:SHL:9) ;- (PMC) Programmab
le Clock Output
277 00000000 00000400
AT91C_PMC_PCK2
EQU (0x1:SHL:10) ;- (PMC) Programma
ble Clock Output
278 00000000 ;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Di
sable Register --------
279 00000000 ;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock St
atus Register --------
280 00000000 ;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillato
r Register --------
281 00000000 ;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Fr
equency Register --------
282 00000000 ;- -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Registe
ARM Macro Assembler Page 16
r --------
283 00000000 ;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock R
egister --------
284 00000000 00000003
AT91C_PMC_CSS
EQU (0x3:SHL:0) ;- (PMC) Programmab
le Clock Selection
285 00000000 00000000
AT91C_PMC_CSS_SLOW_CLK
EQU (0x0) ;- (PMC) Slow Clock
is selected
286 00000000 00000001
AT91C_PMC_CSS_MAIN_CLK
EQU (0x1) ;- (PMC) Main Clock
is selected
287 00000000 00000003
AT91C_PMC_CSS_PLL_CLK
EQU (0x3) ;- (PMC) Clock from
PLL is selected
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