📄 cstartup.lst
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EQU (0x2:SHL:9) ;- (DBGU) Parity fo
rced to 0 (Space)
150 00000000 00000600
AT91C_US_PAR_MARK
EQU (0x3:SHL:9) ;- (DBGU) Parity fo
rced to 1 (Mark)
151 00000000 00000800
AT91C_US_PAR_NONE
EQU (0x4:SHL:9) ;- (DBGU) No Parity
152 00000000 00000C00
AT91C_US_PAR_MULTI_DROP
EQU (0x6:SHL:9) ;- (DBGU) Multi-dro
p mode
153 00000000 0000C000
AT91C_US_CHMODE
EQU (0x3:SHL:14) ;- (DBGU) Channel
Mode
154 00000000 00000000
AT91C_US_CHMODE_NORMAL
ARM Macro Assembler Page 9
EQU (0x0:SHL:14) ;- (DBGU) Normal M
ode: The USART chan
nel operates as an
RX/TX USART.
155 00000000 00004000
AT91C_US_CHMODE_AUTO
EQU (0x1:SHL:14) ;- (DBGU) Automati
c Echo: Receiver Da
ta Input is connect
ed to the TXD pin.
156 00000000 00008000
AT91C_US_CHMODE_LOCAL
EQU (0x2:SHL:14) ;- (DBGU) Local Lo
opback: Transmitter
Output Signal is c
onnected to Receive
r Input Signal.
157 00000000 0000C000
AT91C_US_CHMODE_REMOTE
EQU (0x3:SHL:14) ;- (DBGU) Remote L
oopback: RXD pin is
internally connect
ed to TXD pin.
158 00000000 ;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Int
errupt Enable Register --------
159 00000000 00000001
AT91C_US_RXRDY
EQU (0x1:SHL:0) ;- (DBGU) RXRDY Int
errupt
160 00000000 00000002
AT91C_US_TXRDY
EQU (0x1:SHL:1) ;- (DBGU) TXRDY Int
errupt
161 00000000 00000008
AT91C_US_ENDRX
EQU (0x1:SHL:3) ;- (DBGU) End of Re
ceive Transfer Inte
rrupt
162 00000000 00000010
AT91C_US_ENDTX
EQU (0x1:SHL:4) ;- (DBGU) End of Tr
ansmit Interrupt
163 00000000 00000020
AT91C_US_OVRE
EQU (0x1:SHL:5) ;- (DBGU) Overrun I
nterrupt
164 00000000 00000040
AT91C_US_FRAME
EQU (0x1:SHL:6) ;- (DBGU) Framing E
rror Interrupt
165 00000000 00000080
AT91C_US_PARE
EQU (0x1:SHL:7) ;- (DBGU) Parity Er
ror Interrupt
166 00000000 00000200
AT91C_US_TXEMPTY
EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY I
nterrupt
167 00000000 00000800
ARM Macro Assembler Page 10
AT91C_US_TXBUFE
EQU (0x1:SHL:11) ;- (DBGU) TXBUFE I
nterrupt
168 00000000 00001000
AT91C_US_RXBUFF
EQU (0x1:SHL:12) ;- (DBGU) RXBUFF I
nterrupt
169 00000000 40000000
AT91C_US_COMM_TX
EQU (0x1:SHL:30) ;- (DBGU) COMM_TX
Interrupt
170 00000000 80000000
AT91C_US_COMM_RX
EQU (0x1:SHL:31) ;- (DBGU) COMM_RX
Interrupt
171 00000000 ;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Int
errupt Disable Register --------
172 00000000 ;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit In
terrupt Mask Register --------
173 00000000 ;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Ch
annel Status Register --------
174 00000000 ;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit F
ORCE_NTRST Register --------
175 00000000 00000001
AT91C_US_FORCE_NTRST
EQU (0x1:SHL:0) ;- (DBGU) Force NTR
ST in JTAG
176 00000000
177 00000000 ;- *****************************************************
************************
178 00000000 ;- SOFTWARE API DEFINITION FOR Parallel In
put Output Controler
179 00000000 ;- *****************************************************
************************
180 00000000 ^ 0 ;- AT91S_PIO
181 00000000 00000000
PIO_PER # 4 ;- PIO Enable Regis
ter
182 00000000 00000004
PIO_PDR # 4 ;- PIO Disable Regi
ster
183 00000000 00000008
PIO_PSR # 4 ;- PIO Status Regis
ter
184 00000000 0000000C # 4 ;- Reserved
185 00000000 00000010
PIO_OER # 4 ;- Output Enable Re
gister
186 00000000 00000014
PIO_ODR # 4 ;- Output Disable R
egisterr
187 00000000 00000018
PIO_OSR # 4 ;- Output Status Re
gister
188 00000000 0000001C # 4 ;- Reserved
189 00000000 00000020
PIO_IFER
# 4 ;- Input Filter Ena
ble Register
ARM Macro Assembler Page 11
190 00000000 00000024
PIO_IFDR
# 4 ;- Input Filter Dis
able Register
191 00000000 00000028
PIO_IFSR
# 4 ;- Input Filter Sta
tus Register
192 00000000 0000002C # 4 ;- Reserved
193 00000000 00000030
PIO_SODR
# 4 ;- Set Output Data
Register
194 00000000 00000034
PIO_CODR
# 4 ;- Clear Output Dat
a Register
195 00000000 00000038
PIO_ODSR
# 4 ;- Output Data Stat
us Register
196 00000000 0000003C
PIO_PDSR
# 4 ;- Pin Data Status
Register
197 00000000 00000040
PIO_IER # 4 ;- Interrupt Enable
Register
198 00000000 00000044
PIO_IDR # 4 ;- Interrupt Disabl
e Register
199 00000000 00000048
PIO_IMR # 4 ;- Interrupt Mask R
egister
200 00000000 0000004C
PIO_ISR # 4 ;- Interrupt Status
Register
201 00000000 00000050
PIO_MDER
# 4 ;- Multi-driver Ena
ble Register
202 00000000 00000054
PIO_MDDR
# 4 ;- Multi-driver Dis
able Register
203 00000000 00000058
PIO_MDSR
# 4 ;- Multi-driver Sta
tus Register
204 00000000 0000005C # 4 ;- Reserved
205 00000000 00000060
PIO_PPUDR
# 4 ;- Pull-up Disable
Register
206 00000000 00000064
PIO_PPUER
# 4 ;- Pull-up Enable R
egister
207 00000000 00000068
ARM Macro Assembler Page 12
PIO_PPUSR
# 4 ;- Pull-up Status R
egister
208 00000000 0000006C # 4 ;- Reserved
209 00000000 00000070
PIO_ASR # 4 ;- Select A Registe
r
210 00000000 00000074
PIO_BSR # 4 ;- Select B Registe
r
211 00000000 00000078
PIO_ABSR
# 4 ;- AB Select Status
Register
212 00000000 0000007C # 36 ;- Reserved
213 00000000 000000A0
PIO_OWER
# 4 ;- Output Write Ena
ble Register
214 00000000 000000A4
PIO_OWDR
# 4 ;- Output Write Dis
able Register
215 00000000 000000A8
PIO_OWSR
# 4 ;- Output Write Sta
tus Register
216 00000000
217 00000000 ;- *****************************************************
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