📄 cstartup.lst
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ositive Edge trigge
red
81 00000000 ;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Inte
rrupt Status Register --------
82 00000000 00000001
AT91C_AIC_NFIQ
EQU (0x1:SHL:0) ;- (AIC) NFIQ Statu
s
83 00000000 00000002
AT91C_AIC_NIRQ
ARM Macro Assembler Page 5
EQU (0x1:SHL:1) ;- (AIC) NIRQ Statu
s
84 00000000 ;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Cont
rol Register (Protect) --------
85 00000000 00000001
AT91C_AIC_DCR_PROT
EQU (0x1:SHL:0) ;- (AIC) Protection
Mode
86 00000000 00000002
AT91C_AIC_DCR_GMSK
EQU (0x1:SHL:1) ;- (AIC) General Ma
sk
87 00000000
88 00000000 ;- *****************************************************
************************
89 00000000 ;- SOFTWARE API DEFINITION FOR Peripheral
DMA Controller
90 00000000 ;- *****************************************************
************************
91 00000000 ^ 0 ;- AT91S_PDC
92 00000000 00000000
PDC_RPR # 4 ;- Receive Pointer
Register
93 00000000 00000004
PDC_RCR # 4 ;- Receive Counter
Register
94 00000000 00000008
PDC_TPR # 4 ;- Transmit Pointer
Register
95 00000000 0000000C
PDC_TCR # 4 ;- Transmit Counter
Register
96 00000000 00000010
PDC_RNPR
# 4 ;- Receive Next Poi
nter Register
97 00000000 00000014
PDC_RNCR
# 4 ;- Receive Next Cou
nter Register
98 00000000 00000018
PDC_TNPR
# 4 ;- Transmit Next Po
inter Register
99 00000000 0000001C
PDC_TNCR
# 4 ;- Transmit Next Co
unter Register
100 00000000 00000020
PDC_PTCR
# 4 ;- PDC Transfer Con
trol Register
101 00000000 00000024
PDC_PTSR
# 4 ;- PDC Transfer Sta
tus Register
102 00000000 ;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer C
ontrol Register --------
103 00000000 00000001
ARM Macro Assembler Page 6
AT91C_PDC_RXTEN
EQU (0x1:SHL:0) ;- (PDC) Receiver T
ransfer Enable
104 00000000 00000002
AT91C_PDC_RXTDIS
EQU (0x1:SHL:1) ;- (PDC) Receiver T
ransfer Disable
105 00000000 00000100
AT91C_PDC_TXTEN
EQU (0x1:SHL:8) ;- (PDC) Transmitte
r Transfer Enable
106 00000000 00000200
AT91C_PDC_TXTDIS
EQU (0x1:SHL:9) ;- (PDC) Transmitte
r Transfer Disable
107 00000000 ;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer S
tatus Register --------
108 00000000
109 00000000 ;- *****************************************************
************************
110 00000000 ;- SOFTWARE API DEFINITION FOR Debug Unit
111 00000000 ;- *****************************************************
************************
112 00000000 ^ 0 ;- AT91S_DBGU
113 00000000 00000000
DBGU_CR # 4 ;- Control Register
114 00000000 00000004
DBGU_MR # 4 ;- Mode Register
115 00000000 00000008
DBGU_IER
# 4 ;- Interrupt Enable
Register
116 00000000 0000000C
DBGU_IDR
# 4 ;- Interrupt Disabl
e Register
117 00000000 00000010
DBGU_IMR
# 4 ;- Interrupt Mask R
egister
118 00000000 00000014
DBGU_CSR
# 4 ;- Channel Status R
egister
119 00000000 00000018
DBGU_RHR
# 4 ;- Receiver Holding
Register
120 00000000 0000001C
DBGU_THR
# 4 ;- Transmitter Hold
ing Register
121 00000000 00000020
DBGU_BRGR
# 4 ;- Baud Rate Genera
tor Register
122 00000000 00000024 # 28 ;- Reserved
123 00000000 00000040
ARM Macro Assembler Page 7
DBGU_CIDR
# 4 ;- Chip ID Register
124 00000000 00000044
DBGU_EXID
# 4 ;- Chip ID Extensio
n Register
125 00000000 00000048
DBGU_FNTR
# 4 ;- Force NTRST Regi
ster
126 00000000 0000004C # 180 ;- Reserved
127 00000000 00000100
DBGU_RPR
# 4 ;- Receive Pointer
Register
128 00000000 00000104
DBGU_RCR
# 4 ;- Receive Counter
Register
129 00000000 00000108
DBGU_TPR
# 4 ;- Transmit Pointer
Register
130 00000000 0000010C
DBGU_TCR
# 4 ;- Transmit Counter
Register
131 00000000 00000110
DBGU_RNPR
# 4 ;- Receive Next Poi
nter Register
132 00000000 00000114
DBGU_RNCR
# 4 ;- Receive Next Cou
nter Register
133 00000000 00000118
DBGU_TNPR
# 4 ;- Transmit Next Po
inter Register
134 00000000 0000011C
DBGU_TNCR
# 4 ;- Transmit Next Co
unter Register
135 00000000 00000120
DBGU_PTCR
# 4 ;- PDC Transfer Con
trol Register
136 00000000 00000124
DBGU_PTSR
# 4 ;- PDC Transfer Sta
tus Register
137 00000000 ;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Cont
rol Register --------
138 00000000 00000004
AT91C_US_RSTRX
EQU (0x1:SHL:2) ;- (DBGU) Reset Rec
eiver
139 00000000 00000008
ARM Macro Assembler Page 8
AT91C_US_RSTTX
EQU (0x1:SHL:3) ;- (DBGU) Reset Tra
nsmitter
140 00000000 00000010
AT91C_US_RXEN
EQU (0x1:SHL:4) ;- (DBGU) Receiver
Enable
141 00000000 00000020
AT91C_US_RXDIS
EQU (0x1:SHL:5) ;- (DBGU) Receiver
Disable
142 00000000 00000040
AT91C_US_TXEN
EQU (0x1:SHL:6) ;- (DBGU) Transmitt
er Enable
143 00000000 00000080
AT91C_US_TXDIS
EQU (0x1:SHL:7) ;- (DBGU) Transmitt
er Disable
144 00000000 00000100
AT91C_US_RSTSTA
EQU (0x1:SHL:8) ;- (DBGU) Reset Sta
tus Bits
145 00000000 ;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode
Register --------
146 00000000 00000E00
AT91C_US_PAR
EQU (0x7:SHL:9) ;- (DBGU) Parity ty
pe
147 00000000 00000000
AT91C_US_PAR_EVEN
EQU (0x0:SHL:9) ;- (DBGU) Even Pari
ty
148 00000000 00000200
AT91C_US_PAR_ODD
EQU (0x1:SHL:9) ;- (DBGU) Odd Parit
y
149 00000000 00000400
AT91C_US_PAR_SPACE
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