emhwlib_registers_tango15.h

em86xx 完整启动程序,支持网络下载与串通下载

/******************************************************/
/* This file is generated automatically, DO NOT EDIT! */
/******************************************************/
/*
 * ../emhwlib_hal/include/tango15/emhwlib_registers_tango15.h
 *
 * Copyright (c) 2001-2003 Sigma Designs, Inc. 
 * All Rights Reserved. Proprietary and Confidential.
 *
 */
 
/**
  @file ../emhwlib_hal/include/tango15/emhwlib_registers_tango15.h
  @brief emhwlib generated file
   
  @author Jacques Mahe, Christian Wolff, Julien Soulier, Emmanuel Michon
  @ingroup hwlproperties
*/

#ifndef __EMHWLIB_REGISTERS_TANGO15_H__
#define __EMHWLIB_REGISTERS_TANGO15_H__

/* SystemBlock registers */
#define REG_BASE_system_block 0x00010000 /* width RMuint32 */
#define SYS_clkgen0_pll 0x0000 /* width RMuint32 */
#define SYS_clkgen0_div 0x0004 /* width RMuint32 */
#define SYS_clkgen1_pll 0x0008 /* width RMuint32 */
#define SYS_clkgen1_div 0x000C /* width RMuint32 */
#define SYS_clkgen2_pll 0x0010 /* width RMuint32 */
#define SYS_clkgen2_div 0x0014 /* width RMuint32 */
#define SYS_clkgen3_pll 0x0018 /* width RMuint32 */
#define SYS_clkgen3_div 0x001C /* width RMuint32 */
#define SYS_avclk_mux 0x0038 /* width RMuint32 */
#define SYS_sysclk_mux 0x003C /* width RMuint32 */
#define SYS_clk_cnt 0x0040 /* width RMuint32 */
#define SYS_xtal_in_cnt 0x0048 /* width RMuint32 */
#define DRAM_vbus_w0_cfg 0x0300 /* width RMuint32 */
#define DRAM_vbus_w1_cfg 0x0304 /* width RMuint32 */
#define DRAM_vbus_w2_cfg 0x0308 /* width RMuint32 */
#define DRAM_vbus_w3_cfg 0x030c /* width RMuint32 */
#define DRAM_vbus_r0_cfg 0x0340 /* width RMuint32 */
#define DRAM_vbus_r1_cfg 0x0344 /* width RMuint32 */
#define DRAM_vbus_r2_cfg 0x0348 /* width RMuint32 */
#define DRAM_vbus_r3_cfg 0x034c /* width RMuint32 */
#define DRAM_vbus_r4_cfg 0x0350 /* width RMuint32 */
#define DRAM_vbus_r5_cfg 0x0354 /* width RMuint32 */
#define DRAM_vbus_r6_cfg 0x0358 /* width RMuint32 */
#define DRAM_vbus_r7_cfg 0x035c /* width RMuint32 */
#define DRAM_vbus_r8_cfg 0x0360 /* width RMuint32 */
#define DRAM_vbus_r9_cfg 0x0364 /* width RMuint32 */
#define DRAM_vbus_r10_cfg 0x0368 /* width RMuint32 */
#define DRAM_vbus_r11_cfg 0x036c /* width RMuint32 */
#define DRAM_mbus_w0_cfg 0x0200 /* width RMuint32 */
#define DRAM_mbus_w1_cfg 0x0204 /* width RMuint32 */
#define DRAM_mbus_w2_cfg 0x0208 /* width RMuint32 */
#define DRAM_mbus_w3_cfg 0x020c /* width RMuint32 */
#define DRAM_mbus_w4_cfg 0x0210 /* width RMuint32 */
#define DRAM_mbus_w5_cfg 0x0214 /* width RMuint32 */
#define DRAM_mbus_w6_cfg 0x0218 /* width RMuint32 */
#define DRAM_mbus_w7_cfg 0x021c /* width RMuint32 */
#define DRAM_mbus_w8_cfg 0x0220 /* width RMuint32 */
#define DRAM_mbus_w9_cfg 0x0224 /* width RMuint32 */
#define DRAM_mbus_w10_cfg 0x0228 /* width RMuint32 */
#define DRAM_mbus_r0_cfg 0x0240 /* width RMuint32 */
#define DRAM_mbus_r1_cfg 0x0244 /* width RMuint32 */
#define DRAM_mbus_r2_cfg 0x0248 /* width RMuint32 */
#define DRAM_mbus_r3_cfg 0x024c /* width RMuint32 */
#define DRAM_mbus_r4_cfg 0x0250 /* width RMuint32 */
#define DRAM_mbus_r5_cfg 0x0254 /* width RMuint32 */
#define DRAM_mbus_r6_cfg 0x0258 /* width RMuint32 */
#define DRAM_mbus_r7_cfg 0x025c /* width RMuint32 */
#define DRAM_mbus_r8_cfg 0x0260 /* width RMuint32 */
#define DRAM_mbus_r9_cfg 0x0264 /* width RMuint32 */
#define DRAM_mbus_r10_cfg 0x0268 /* width RMuint32 */
#define SYS_vcxo0_cnt 0x0050 /* width RMuint32 */
#define SYS_vcxo1_cnt 0x0058 /* width RMuint32 */
#define SYS_rclk_out_cnt 0x0060 /* width RMuint32 */
#define SYS_sel_clk_cnt 0x0068 /* width RMuint32 */
#define SYS_cleandiv0_div 0x0080 /* width RMuint32 */
#define SYS_cleandiv1_div 0x0090 /* width RMuint32 */
#define SYS_cleandiv2_div 0x00a0 /* width RMuint32 */
#define SYS_cleandiv3_div 0x00b0 /* width RMuint32 */
#define MARB_mid01_cfg 0x0200 /* width RMuint32 */
#define MARB_mid21_cfg 0x0204 /* width RMuint32 */
#define MARB_mid02_cfg 0x0208 /* width RMuint32 */
#define MARB_mid22_cfg 0x020c /* width RMuint32 */
#define MARB_mid04_cfg 0x0210 /* width RMuint32 */
#define MARB_mid24_cfg 0x0214 /* width RMuint32 */
#define MARB_mid25_cfg 0x0218 /* width RMuint32 */
#define MARB_mid08_cfg 0x021c /* width RMuint32 */
#define MARB_mid28_cfg 0x0220 /* width RMuint32 */
#define MARB_mid29_cfg 0x0224 /* width RMuint32 */
#define MARB_mid0C_cfg 0x0228 /* width RMuint32 */
#define MARB_mid2C_cfg 0x022c /* width RMuint32 */
#define MARB_mid10_cfg 0x0230 /* width RMuint32 */
#define MARB_mid30_cfg 0x0234 /* width RMuint32 */
#define MARB_mid31_cfg 0x0238 /* width RMuint32 */
#define MARB_mid12_cfg 0x023c /* width RMuint32 */
#define MARB_mid32_cfg 0x0240 /* width RMuint32 */
#define VARB_mid01_cfg 0x0300 /* width RMuint32 */
#define VARB_mid02_cfg 0x0304 /* width RMuint32 */
#define VARB_mid21_cfg 0x0308 /* width RMuint32 */
#define VARB_mid22_cfg 0x030c /* width RMuint32 */
#define VARB_mid23_cfg 0x0310 /* width RMuint32 */
#define VARB_mid24_cfg 0x0314 /* width RMuint32 */
#define VARB_mid25_cfg 0x0318 /* width RMuint32 */
#define VARB_mid26_cfg 0x031c /* width RMuint32 */
#define VARB_mid27_cfg 0x0320 /* width RMuint32 */
#define VARB_mid28_cfg 0x0324 /* width RMuint32 */
#define VARB_mid29_cfg 0x0328 /* width RMuint32 */
#define VARB_mid2A_cfg 0x032c /* width RMuint32 */
#define VARB_mid10_cfg 0x0330 /* width RMuint32 */
#define VARB_mid30_cfg 0x0334 /* width RMuint32 */
#define VARB_mid31_cfg 0x0338 /* width RMuint32 */
#define IARB_mid01_cfg 0x0400 /* width RMuint32 */
#define IARB_mid02_cfg 0x0404 /* width RMuint32 */
#define SYS_gpio_dir 0x0500 /* width RMuint32 */
#define SYS_gpio_data 0x0504 /* width RMuint32 */
#define SYS_gpio_int 0x0508 /* width RMuint32 */
#define SYS_gpio15_pwm 0x0510 /* width RMuint32 */
#define SYS_gpio14_pwm 0x0514 /* width RMuint32 */
#define REG_BASE_dram_controller_0 0x00030000 /* width RMuint32 */
#define MEM_BASE_dram_controller_0 0x10000000 /* width RMuint32 */
#define REG_BASE_dram_controller_1 0x00040000 /* width RMuint32 */
#define MEM_BASE_dram_controller_1 0x20000000 /* width RMuint32 */
#define REG_BASE_dram_controller_2 0x00050000 /* width RMuint32 */
#define MEM_BASE_dram_controller_2 0x30000000 /* width RMuint32 */
#define DRAM_dunit_cfg 0x0000 /* width RMuint32 */
#define DRAM_dunit_delay0_ctrl 0x0004 /* width RMuint32 */
#define DRAM_dunit_delay1_ctrl 0x0008 /* width RMuint32 */
#define DRAM_dunit_auto_delay 0x000c /* width RMuint32 */
#define DRAM_dunit_delay_probe 0x0010 /* width RMuint32 */
#define DRAM_dunit_effective_delay 0x0014 /* width RMuint32 */
#define DRAM_dunit_bw_probe_cfg 0x0020 /* width RMuint32 */
#define DRAM_dunit_bw_probe_cnt 0x0024 /* width RMuint32 */
#define DRAM_dunit_flush_buffer 0x0104 /* width RMuint32 */
#define REG_BASE_host_interface 0x00020000 /* width RMuint32 */
#define MEM_BASE_host_interface 0x40000000 /* width RMuint32 */
#define IDE_data 0x0000 /* width RMuint32 */
#define IDE_error 0x0004 /* width RMuint32 */
#define IDE_count 0x0008 /* width RMuint32 */
#define IDE_start_sector 0x000c /* width RMuint32 */
#define IDE_cylinder_lo 0x0010 /* width RMuint32 */
#define IDE_cylinder_hi 0x0014 /* width RMuint32 */
#define IDE_head_device 0x0018 /* width RMuint32 */
#define IDE_cmd_stat 0x001c /* width RMuint32 */
#define IDE_irq_stat 0x0218 /* width RMuint32 */
#define IDE_cmd_stat__ 0x021c /* width RMuint32 */
#define PB_timing0 0x0800 /* width RMuint32 */
#define PB_timing1 0x0804 /* width RMuint32 */
#define PB_timing2 0x0808 /* width RMuint32 */
#define PB_timing3 0x080c /* width RMuint32 */
#define PB_timing4 0x0810 /* width RMuint32 */
#define PB_timing5 0x0814 /* width RMuint32 */
#define PB_default_timing 0x0818 /* width RMuint32 */
#define PB_use_timing0 0x081c /* width RMuint32 */
#define PB_use_timing1 0x0820 /* width RMuint32 */
#define PB_use_timing2 0x0824 /* width RMuint32 */
#define PB_use_timing3 0x0828 /* width RMuint32 */
#define PB_use_timing4 0x082c /* width RMuint32 */
#define PB_use_timing5 0x0830 /* width RMuint32 */
#define PB_CS_config 0x0834 /* width RMuint32 */
#define PB_automode_start_address 0x0840 /* width RMuint32 */
#define PB_automode_control 0x0844 /* width RMuint32 */
#define SFLA_status 0xa000 /* width RMuint32 */
#define SFLA_read_parameters 0xa008 /* width RMuint32 */
#define SFLA_drive_pads 0xa00c /* width RMuint32 */
#define SFLA_driver_speed 0xa010 /* width RMuint32 */
#define SFLA_N_for_Send_Get 0xa020 /* width RMuint32 */
#define SFLA_read_data 0xa030 /* width RMuint32 */
#define SFLA_Send_1 0xa040 /* width RMuint32 */
#define SFLA_Send_8 0xa044 /* width RMuint32 */
#define SFLA_Send_16 0xa048 /* width RMuint32 */
#define SFLA_Send_32 0xa04c /* width RMuint32 */
#define SFLA_Send_Get_1 0xa050 /* width RMuint32 */
#define SFLA_Send_Get_8 0xa054 /* width RMuint32 */
#define SFLA_Send_Get_16 0xa058 /* width RMuint32 */
#define SFLA_Send_Get_32 0xa05c /* width RMuint32 */
#define SFLA_Chip_Select 0xa060 /* width RMuint32 */
#define SFLA_Chip_Deselect 0xa064 /* width RMuint32 */
#define SFLA_Send_N 0xa068 /* width RMuint32 */
#define SFLA_Get_SlaveOut 0xa070 /* width RMuint32 */
#define SFLA_Wait_Timer 0xa074 /* width RMuint32 */
#define SFLA_Send_Get_N 0xa078 /* width RMuint32 */
#define EMHWLIB_IS_HOST 0xe000 /* width RMuint32 */
#define HOST_REG1 0xfed0 /* width RMuint32 */
#define HOST_REG2 0xfed4 /* width RMuint32 */
#define READ_ADDRESS 0xfec0 /* width RMuint32 */
#define READ_COUNTER 0xfec4 /* width RMuint32 */
#define READ_ENABLE 0xfec8 /* width RMuint32 */
#define READ_REVERSE 0xfecc /* width RMuint32 */
#define WRITE_ADDRESS 0xfed8 /* width RMuint32 */
#define WRITE_COUNTER 0xfedc /* width RMuint32 */
#define WRITE_ENABLE 0xfee0 /* width RMuint32 */
#define BURST 0xfee4 /* width RMuint32 */
#define PCI_TIMEOUT 0x8000 /* width RMuint32 */
#define PCI_TIMEOUT_STATUS 0x8004 /* width RMuint32 */
#define PCI_TIMER 0x8008 /* width RMuint32 */
#define PCI_TIMER_TEST 0x800c /* width RMuint32 */
#define PCI_WAKEUP 0x8010 /* width RMuint32 */
#define PCI_REGION_0_BASE 0x9000 /* width RMuint32 */
#define PCI_REGION_1_BASE 0x9004 /* width RMuint32 */
#define PCI_REGION_2_BASE 0x9008 /* width RMuint32 */
#define PCI_REGION_3_BASE 0x900c /* width RMuint32 */
#define PCI_REGION_4_BASE 0x9010 /* width RMuint32 */
#define PCI_REGION_5_BASE 0x9014 /* width RMuint32 */
#define PCI_REGION_6_BASE 0x9018 /* width RMuint32 */
#define PCI_REGION_7_BASE 0x901c /* width RMuint32 */
#define PCI_irq_status 0x9020 /* width RMuint32 */
#define PCI_irq_set 0x9024 /* width RMuint32 */
#define PCI_irq_clear 0x9028 /* width RMuint32 */
#define SBOX_FIFO_RESET 0x90a0 /* width RMuint32 */
#define SBOX_ROUTE 0x90a8 /* width RMuint32 */
#define output_SBOX_MBUS_W0 0x9080 /* width RMuint32 */
#define output_SBOX_MBUS_W1 0x9084 /* width RMuint32 */
#define output_SBOX_PCI_MASTER 0x9088 /* width RMuint32 */
#define output_SBOX_PCI_SLAVE 0x908c /* width RMuint32 */
#define output_SBOX_CIPHER 0x9090 /* width RMuint32 */
#define output_SBOX_IDE_ISA 0x9094 /* width RMuint32 */
#define output_SBOX_IDE_DVD 0x9098 /* width RMuint32 */
#define input_keep_SBOX 0 /* width RMuint32 */
#define input_MBUS_R0_SBOX 1 /* width RMuint32 */
#define input_MBUS_R1_SBOX 2 /* width RMuint32 */
#define input_PCI_MASTER_SBOX 3 /* width RMuint32 */
#define input_PCI_SLAVE_SBOX 4 /* width RMuint32 */
#define input_CIPHER_SBOX 5 /* width RMuint32 */
#define input_IDE_DVD_SBOX 6 /* width RMuint32 */
#define input_IDE_ISA_SBOX 7 /* width RMuint32 */
#define input_SFLA_SBOX 8 /* width RMuint32 */
#define input_unconnected_SBOX 0xf /* width RMuint32 */
#define host_mutex0 0x9040 /* width RMuint32 */
#define host_mutex1 0x9044 /* width RMuint32 */
#define host_mutex2 0x9048 /* width RMuint32 */
#define host_mutex3 0x904c /* width RMuint32 */
#define host_mutex4 0x9050 /* width RMuint32 */
#define host_mutex5 0x9054 /* width RMuint32 */
#define host_mutex6 0x9058 /* width RMuint32 */
#define host_mutex7 0x905c /* width RMuint32 */
#define host_mutex8 0x9060 /* width RMuint32 */
#define host_mutex9 0x9064 /* width RMuint32 */
#define host_mutex10 0x9068 /* width RMuint32 */
#define host_mutex11 0x906c /* width RMuint32 */
#define host_mutex12 0x9070 /* width RMuint32 */
#define host_mutex13 0x9074 /* width RMuint32 */
#define host_mutex14 0x9078 /* width RMuint32 */
#define host_mutex15 0x907c /* width RMuint32 */
#define PCI_chip_is_host 0xfe90 /* width RMuint32 */
#define IDECTRL_idesrc 0x20d0 /* width RMuint32 */