loader-flash-xtra0.s

em86xx 完整启动程序,支持网络下载与串通下载

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# 38 "memcfg.h"



# 29 "loader-stage0.S" 2





 




 








    .text
    .code 32
    .align 0

    .global stage0_start

# 66 "loader-stage0.S"


    b   stage0_start            @ offset 0x00

@
@ user configurable settings : 0x60 - 4
@

config_start:

data_filesize:                  @ offset 0x04 : stage 1 boot loader size
    .long 0x00000000
data_version:                   @ offset 0x08
 
    .long ((( 0 ) << 16) | ((  12 ) << 8) | (  17 ))  
data_signature:                 @ offset 0x0c
    .long 0x424d414d 

data_SYS_clkgen0_pll:           @ offset 0x10
                                @ FIN = 27000000  (e.g. 27000000)
                                @ clock = (FIN * (N + 2) / (M + 2)) / 2
    @ .long 0x0101002e          @ (46 + 2) / (1 + 2) = 16 : FIN * 16 / 2 = 216.0 MHz
    @ .long 0x0101002b          @ (43 + 2) / (1 + 2) = 15 : FIN * 15 / 2 = 202.5 MHz
    @ .long 0x01010028          @ (40 + 2) / (1 + 2) = 14 : FIN * 14 / 2 = 189.0 MHz
    @ .long 0x01010025          @ (37 + 2) / (1 + 2) = 13 : FIN * 13 / 2 = 175.5 MHz
    @ .long 0x01010022          @ (34 + 2) / (1 + 2) = 12 : FIN * 12 / 2 = 162.0 MHz
    @ .long 0x0101001f          @ (31 + 2) / (1 + 2) = 11 : FIN * 11 / 2 = 148.5 MHz
    @ .long 0x0101001c          @ (28 + 2) / (1 + 2) = 10 : FIN * 10 / 2 = 135.0 MHz
    @ .long 0x01010019          @ (25 + 2) / (1 + 2) = 9 : FIN * 9 / 2 = 121.5 MHz
    @ .long 0x01010016          @ (22 + 2) / (1 + 2) = 8 : FIN * 8 / 2 = 108.0 MHz
    .long 0x0101002a 
data_DRAM0_dunit_cfg:           @ offset 0x14
    @ .long 0xe34000b8
    .long 0xf63001f8 
data_DRAM1_dunit_cfg:           @ offset 0x18
    @ .long 0xe34000b8
    @ .long 0x133000bc
    @ .long 0x0
    .long 0 
data_DRAM_dunit_delay0_ctrl:    @ offset 0x1c
    .long 0x00084454 





data_pb_default_timing:         @ offset 0x20
    .long 0x10101010 




data_pci_subsystem_id:          @ offset 0x24
    .long 0x00000000 
data_pci_revision_id:           @ offset 0x28
    .long 0    @ Rev. A = 1, Rev. B = 2
data_pci_memory_size:           @ offset 0x2c
    .long 0 

data_bootflag:                  @ offset 0x30
    @.long 0x00 
    @.long (0x01  | (( 0x02  ) << 2) )
    @.long (0x01  | (( 0x01  ) << 2)  | (( 0x02  ) << 6) )
    @.long (0x01  | (( 0x03  ) << 2) )
    .long 0x00  

data_configvalid:               @ offset 0x34
    .long (1 << 0)  

data_dramsize:                  @ offset 0x38
    .long ((  5   )  | ((   0   ) << 8) ) 

data_imagesize:                 @ offset 0x3c : entire image size except serial flash signature
    .long 0x00000000
data_checksum:                  @ offset 0x40 : checksum 
    .long 0x00000000



data_other_config:              @ offset 0x44 - 0x4f
    .long 0x00000000
    .long 0x00000000
    .long 0x00000000

data_boardname:                 @ offset 0x50 - 0x5f




    .space 0x10, 0x00



config_end:

@
@ debugging
@
@ uart_init : initialize UART 0
@ uart_putc : print out one character (debug, production test)
@ uart_putc_debug : print out one character (debug only)
@


    .equ    UART_INTEN, 0x08
    .equ    UART_FIFOCTL, 0x10
    .equ    UART_LINECTL, 0x14
    .equ    UART_CLKDIV, 0x28
    .equ    UART_CLKSEL, 0x2c

    .macro uart_init, reg1, reg2
    ldr \reg1, =(0x00060000   + 0xc100 )
    mov \reg2, #0x00            @ disable interrupt
    str \reg2, [\reg1, #UART_INTEN]
    mov \reg2, #0x1f
    str \reg2, [\reg1, #UART_FIFOCTL]
    mov \reg2, #0x03            @ N-8-1
    str \reg2, [\reg1, #UART_LINECTL]



    mov \reg2, #0x01            @ external clock

    str \reg2, [\reg1, #UART_CLKSEL]
# 200 "loader-stage0.S"


    mov \reg2, #((27000000 ) /(16* 57600 ))





    str \reg2, [\reg1, #UART_CLKDIV]
    .endm

    .macro uart_putc, ch, reg1, reg2







    ldr \reg1, =(0x00060000   + (0xc100  + 0x04) )
    mov \reg2, \ch
    str \reg2, [\reg1]
    .endm

    .macro uart_putc_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm
# 237 "loader-stage0.S"



    .macro uart_putc_debug_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm





@
@ initialize Serial Flash & PLL
@ After hard reset, CPU operates at 13.5MHz
@

stage0_start:
    @ internally use :
    @  r0, r1 : register
    @  r2 : data







    @ set periphal bus default timing compatible with high CPU clock
    ldr r0, =(0x00020000   + 0x0818 )
    ldr r2, data_pb_default_timing
    str r2, [r0]


    @ set PLL
    ldr r1, =(0x00010000   + 0x0000 )
    ldr r2, data_SYS_clkgen0_pll
    str r2, [r1]

    @ set clock MUX
    ldr r1, =(0x00010000   + 0x003C )
    mov r2, #1
    str r2, [r1]

    @ invalidate and disable caches
    mov r0, #0x00
    mcr p15, 0x0, r0, c7, c5, 0     @ Invalidate Instruction Cache (all)
    mcr p15, 0x0, r0, c7, c6, 0     @ Invalidate Data Cache (all)
    mcr p15, 0x0, r0, c1, c0, 0     @ disable all cache

    @ setup initial fiq stack top
setup_fiq_stack:
    mrs r1, cpsr		    @ save old cpsr
    msr cpsr_c, #0xd1		    @ FIQ mode, disable IRQ/FIQ
    ldr r0, =(0x90000000  + 0x00050000 ) @ growing downward
    mov sp, r0			    @ set stack
    msr cpsr_c, r1		    @ restore old cpsr

# 350 "loader-stage0.S"



    @ nop cycles for stability (not necessary)
    mov r0, r0
    mov r0, r0
    mov r0, r0
    mov r0, r0


@
@ initialize DRAM
@

dram_init:

    uart_init r10, r11
    uart_putc #'D', r10, r11

    @ initialize DRAM controller 0
    uart_putc_io #'1', r10, r11
    mov r0, #0x00030000  
    ldr r1, data_DRAM0_dunit_cfg
    ldr r2, data_DRAM_dunit_delay0_ctrl
    bl dram_init_ctrl

    @ initialize DRAM controller 1
    uart_putc_io #'2', r10, r11
    mov r0, #0x00040000  
    ldr r1, data_DRAM1_dunit_cfg
    bl dram_init_ctrl

    b cache_init

dram_init_ctrl:
    @ initialize each DRAM controller
    @ call with :
    @  r0 = base address of DRAM controller register
    @  r1 = setting for 0x0000 
    @    if this setting is 0, just disable the DRAM controller
    @  r2 = setting for 0x0004 
    @ internally use :
    @  r3, r4 : register
    @  r5 : data

    @ reset
    add r3, r0, #0xff00 
    add r3, r3, #((0xff00  + 0xfc)  - 0xff00 )
    mov r5, #0x03
    strb r5, [r3]
    cmp r1, #0x00       @ if the DRAM should be disabled
    moveq pc, lr        @ just return here
    mov r5, #0x02
    strb r5, [r3]

    @ DRAM configuration
    add r4, r0, #0x0000 
    str r1, [r4]

    @ DRAM delay control
    add r4, r0, #0x0004 
    str r2, [r4]

    @ full operation
    mov r5, #0x00
    strb r5, [r3]

    @ return to caller
    mov pc, lr

@
@ cache control
@

cache_init:

    uart_putc_io #'C', r10, r11


    mov r0, #0x1c                   @ 512 MB regions (0x10000000)
    orr r0, r0, r0, lsl #8          @ Instruction and Data region size
    mcr p15, 0x0, r0, c6, c0, 0     @ Region Size register (CP15-6)

    mov r0, #0xf000                 @ Enable Instruction Cache for regions over 2GB (4, 5, 6, 7)
    orr r0, r0, #0x00f0             @ Enable Data Cache for regions over 2GB (4, 5, 6, 7)
    mcr p15, 0x0, r0, c2, c0, 0     @ Cacheability Control register (CP15-2)

    mov r0, #0xf0                   @ Enable Writeback for regions over 2GB (4, 5, 6, 7)
    mcr p15, 0x0, r0, c3, c0, 0     @ Writeback Control register (CP15-3)

    ldr r0, =0xffff                 @ Read/write access in any mode
    mcr p15, 0x0, r0, c4, c0, 0     @ Instruction Space Protection register (CP15-4)

    ldr r0, =0xffff                 @ Read/write access in any mode
    mcr p15, 0x0, r0, c5, c0, 0     @ Data Space Protection register (CP15-5)

    mov r0, #0x00                   @ (little-endian)
    orr r0, r0, #0x1000             @ Instruction Cache Enable
    orr r0, r0, #0x0004             @ Data Cache Enable
    orr r0, r0, #0x0002             @ Write Buffering
    orr r0, r0, #0x0001             @ Protection Enable
                                    @ When set, this bit enables caches, protection,
                                    @ and write buffering. When cleared, all are disabled
                                    @ regardless of other bits.
    mcr p15, 0x0, r0, c1, c0, 0     @ Configuration register (CP15-1)

    @ nop cycles for stability (not necessary)
    mov r0, r0
    mov r0, r0
    mov r0, r0
    mov r0, r0


@
@ do other initialization
@

misc_init:

# 561 "loader-stage0.S"


@
@ DRAM adjustment
@


    uart_putc_io #'M', r10, r11

    @ setup stack for C codes
    @ EM86XX has internal memory at 0x00060000  
    @ use internal memory for stack of C functions
    ldr r1, =(0x00060000   + (0x000017F4 ) )
    mov sp, r1

    @ call xtra_stage0() function
    ldr r0, =((((0x44000000  + (0x01000000 * ( 2  ))) )  ) )       @ first parameter
    ldr r1, =((((0x44000000  + (0x01000000 * ( 2  ))) )   + 0x400 ) )  @ new PC
    orr r1, r1, #0x80000000		@ jump to cache-on area
    mov lr, pc
    mov pc, r1                          @ emulate 'bl' instruction

    uart_putc #'m', r10, r11


@
@ Crypto stage 0
@

# 619 "loader-stage0.S"


@
@ production test
@

# 642 "loader-stage0.S"


@
@ load main boot loader to DRAM
@
















    @ copy boot loader
load_to_dram:









# 745 "loader-stage0.S"


stage1_load:
    uart_putc_debug_io #'L', r10, r11

    @ load addresses
    adr r0, load_addr
    @ldmia r0, { r1 - r3 }
    ldr r1, [r0, #0x00]     @ STAGE1 image start address
    ldr r2, [r0, #0x04]     @ STAGE1 image end address
    ldr r3, [r0, #0x08]     @ address where loader copys STAGE1 image to

    ldr r4, data_filesize
    cmp r4, #0x00
    addne r2, r1, r4





    bl copy_func


    mov r9, #0

    @ copy configuration
load_config_to_dram:

    uart_putc_debug_io #'F', r10, r11

    adr r1, config_start
    adr r2, config_end










1:
    ldr r3, = (0x90060000  + 0x40)  

2:



    ldr r4, = 0x414c4650 



    str r4, [r3], #4





    bl copy_func


@
@ jump to boot loader in the RAM
@

boot_main:

    uart_putc_debug_io #'J', r10, r11
    uart_putc_debug_io #'{', r10, r11
    uart_putc_debug_io #'}', r10, r11
    #uart_putc_debug_io #'\r', r10, r11
    #uart_putc_debug_io #'\n', r10, r11

# 827 "loader-stage0.S"


3:
    adr r0, load_addr		@ get stage1 entry point
    ldr r9, [r0, #0x0c]

4:
    mov pc, r9

load_addr:
    .long (((0x44000000  + (0x01000000 * ( 2  ))) )   + (0x400  + 0  + 2048 ) ) 
    .long (((0x44000000  + (0x01000000 * ( 2  ))) )   + 0x20000 ) 
    .long 0x90060000  
    .long 0x90060000  

copy_func:
    @ r1 = src, r2 = end of source, r3 = des
    @ destroy r4
    uart_putc_debug_io #'c', r10, r11
copy_func_loop:
    @ldmia r1!, { r4 - r7 }
    @stmia r3!, { r4 - r7 }
    ldr r4, [r1], #4
    str r4, [r3], #4
    cmp r1, r2
    blt copy_func_loop

    mov pc, lr
copy_func_end: