test-stage0.c

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/* Special mode starts here */
static unsigned long hexStringToULong(const char *str, int size)
{
    unsigned long res = 0;
    int base = 10;
    int i;

    if ((*str == '0') && ((*(str + 1) == 'x') || (*(str + 1) == 'X'))) {
	 base = 16;
	 str += 2;
    }

    for (i = 0; (*str != '\0') && (i < size); str++, i++) {
	 if ((*str >= '0') && (*str <= '9'))
	     res = (res * base) + (*str - '0');
	 else if (base == 16) {
		 if ((*str >= 'a') && (*str <= 'f'))
			 res = (res * base) + 10 + (*str - 'a');
		 else if ((*str >= 'A') && (*str <= 'F'))
			 res = (res * base) + 10 + (*str - 'A');
		 else
			 return(0);
	 } else 
		 return(0);
    }
    return(res);
}

static unsigned long uart_getULong(char *prompt)
{
    unsigned long res;
    char buf[64];
    uart_puts(prompt);
    uart_gets(buf, 64, 1);
    res = hexStringToULong(buf, 64);
    return(res);
}

unsigned long tango_get_sysclock(void)
{
    unsigned long sys_clkgen_pll, sysclk_mux, n, m, freq;
    sys_clkgen_pll = gbus_read_uint32(0, REG_BASE_system_block + SYS_clkgen0_pll);
    sysclk_mux = gbus_read_uint32(0, REG_BASE_system_block + SYS_sysclk_mux);
    n = sys_clkgen_pll & 0x000003ff;
    m = (sys_clkgen_pll & 0x003f0000) >> 16;

    if (sysclk_mux & 0x1) 	/* PLL is used */
	freq = idivide(EM86XX_EXT_CLOCK, m + 2) * (n + 2);
    else
	freq = EM86XX_EXT_CLOCK;
    return(freq >> 1);
}

static int stage0_special_mode(void)
{
    char c;
    int done = 0;

    int start = DEFAULT_FREQ_START;
    int end = DEFAULT_FREQ_END;
    int w_delay = DEFAULT_WRITE_DELAY;
    int mem_test_needed = 0;
    int dunit_changed = 0;
    int def_freq;
    unsigned long pll;

    pll = gbus_read_uint32(0, REG_BASE_system_block + SYS_clkgen0_pll);
    def_freq = DEFAULT_FREQ_ALL_BIT;

    uart_puts("\n\n");
    while (done == 0) {
	uart_puts("Special Mode Menu:\n");
	uart_printf("\t[0] Set DRAM0 dunit_cfg (0x%08lx)\n", gbus_read_uint32(0, REG_BASE_dram_controller_0 + DRAM_dunit_cfg));
#if (DEFAULT_DRAM1_SIZE != 0)
	uart_printf("\t[1] Set DRAM1 dunit_cfg (0x%08lx)\n", gbus_read_uint32(0, REG_BASE_dram_controller_1 + DRAM_dunit_cfg));
#endif
	uart_printf("\t[S] Set DRAM Test start frequency (%dMHz)\n", start);
	uart_printf("\t[E] Set DRAM Test end frequency (%dMHz)\n", end);
	uart_printf("\t[L] Set DRAM Test write delay (%d)\n", w_delay);
	uart_puts("\t[D] Start DRAM Test\n");
	uart_puts("\t[3] GR32\n");
	uart_puts("\t[4] GW32\n");
	uart_puts("\t[6] GR16\n");
	uart_puts("\t[7] GW16\n");
	uart_puts("\t[8] GR8\n");
	uart_puts("\t[9] GW8\n");
	uart_printf("\t[F] Set System frequency (SYS: %dMHz)\n", idivide(tango_get_sysclock(), 1000000));
	uart_puts("\t[X] Exit special mode\n");
	uart_puts("\tChoice: ");

	c = uart_getc();
	uart_putc('\n');
	switch(c) {
	    case '0': {
			 unsigned long dunit_cfg, delay;
			 dunit_cfg = uart_getULong("  DRAM0 dunit_cfg: ");
			 if (dunit_cfg != 0) {
				 delay = gbus_read_uint32(0, REG_BASE_dram_controller_0 + DRAM_dunit_delay0_ctrl);
				 gbus_write_uint32(0, REG_BASE_dram_controller_0 + G2L_RESET_CONTROL, 3);
				 gbus_write_uint32(0, REG_BASE_dram_controller_0 + G2L_RESET_CONTROL, 2);
				 gbus_write_uint32(0, REG_BASE_dram_controller_0 + DRAM_dunit_cfg, dunit_cfg);
				 gbus_write_uint32(0, REG_BASE_dram_controller_0 + DRAM_dunit_delay0_ctrl, delay);
				 gbus_write_uint32(0, REG_BASE_dram_controller_0 + G2L_RESET_CONTROL, 0);
				 dunit_changed = 1;
			 } else 
				 uart_puts("  Invalid input value.\n");
	            }
		    break;
#if (DEFAULT_DRAM1_SIZE != 0)
	    case '1': {
			 unsigned long dunit_cfg, delay;
			 dunit_cfg = uart_getULong("  DRAM1 dunit_cfg: ");
			 if (dunit_cfg != 0) {
				 delay = gbus_read_uint32(0, REG_BASE_dram_controller_1 + DRAM_dunit_delay0_ctrl);
				 gbus_write_uint32(0, REG_BASE_dram_controller_1 + G2L_RESET_CONTROL, 3);
				 gbus_write_uint32(0, REG_BASE_dram_controller_1 + G2L_RESET_CONTROL, 2);
				 gbus_write_uint32(0, REG_BASE_dram_controller_1 + DRAM_dunit_cfg, dunit_cfg);
				 gbus_write_uint32(0, REG_BASE_dram_controller_1 + DRAM_dunit_delay0_ctrl, delay);
				 gbus_write_uint32(0, REG_BASE_dram_controller_1 + G2L_RESET_CONTROL, 0);
				 dunit_changed = 1;
			 } else 
				 uart_puts("  Invalid input value.\n");
	            }
		    break;
#endif
	    case 'S':
	    case 's': {
			 unsigned long val = uart_getULong("  DRAM Test Start freq.: ");
			 if (val == 0) 
				 uart_puts("  Invalid input value.\n");
			 else if (val > end)
				 uart_printf("  Invalid value %ld (start > end)\n", val);
			 else 
				 start = val;
	            }
		    break;
	    case 'E':
	    case 'e': {
			 unsigned long val = uart_getULong("  DRAM Test End freq.: ");
			 if (val == 0) 
				 uart_puts("  Invalid input value.\n");
			 else if (val < start)
				 uart_printf("  Invalid value %ld (end < start)\n", val);
			 else 
				 end = val;
	            }
		    break;
	    case 'L':
	    case 'l': { 
			 unsigned long val = uart_getULong("  DRAM Test Write delay: ");
			 if (val >= 0x10)
				 uart_printf("  Invalid input value %ld (0x%lx).\n", val, val);
			 else 
				 w_delay = val;
	            }
		    break;
	    case 'D':
            case 'd':
		    uart_puts("\n\n");
		    em8600_mem_test(start, end, w_delay, def_freq, 0, dunit_changed);
		    dunit_changed = mem_test_needed = 0;
		    uart_puts("\n\n");
		    break;
            case '3': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 4): ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%08lx\n", gbus_addr, gbus_read_uint32(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '4': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 4): ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ");
				  gbus_write_uint32(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%08lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '6': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 2): ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%04lx\n", gbus_addr, gbus_read_uint16(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '7': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 2): ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ") & 0xffff;
				  gbus_write_uint16(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%04lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '8': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address: ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%02lx\n", gbus_addr, gbus_read_uint8(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '9': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address: ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ") & 0xff;
				  gbus_write_uint8(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%02lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
	    case 'F':
            case 'f': {
			  unsigned long freq, mux, fp_divider = 0;

			  freq = uart_getULong("  System freq.: ");

			  if (freq == 0) {
				 uart_puts("  Invalid input value.\n");
				 break;
			  }

			  mux = gbus_read_uint32(0, REG_BASE_system_block + SYS_sysclk_mux);
			  switch((mux >> 8) & 0xf) {
				  case 0: fp_divider = 0x1190000;
					  break;
				  case 2:
				  case 3:
				  case 4:
				  case 5:
				  case 6:
				  case 7: fp_divider = 0x1100000;
					  break;
				  default: uart_puts("No supported divider value.\n");
					   done = 1;
					   break;
			  }

			  gbus_write_uint32(0, REG_BASE_system_block + SYS_sysclk_mux, 
					  gbus_read_uint32(0, REG_BASE_system_block + SYS_sysclk_mux) & 0xfffffffe);
			  gbus_write_uint32(0, REG_BASE_system_block + SYS_clkgen0_pll, fp_divider + ((freq << 1) - 2));
			  gbus_write_uint32(0, REG_BASE_system_block + SYS_sysclk_mux, mux);
			  em86xx_msleep(100);
			  freq = idivide(tango_get_sysclock(), 1000000);
			  uart_printf("\nSystem frequency is now %dMHz.\n", freq);
			  def_freq = freq;
			  mem_test_needed = 1;
			  if (freq < start) {
				  start = freq - 12;
				  end = freq + 28;
			  }
			  if (freq > end) {
				  end = freq + 12;
				  start = freq - 28;
			  }
	            }
		    break;
	    case 'X':
            case 'x':
		    uart_puts("Exiting special mode.\n");
		    done = 1;
		    break;
        }
    }

    if ((mem_test_needed != 0) || (dunit_changed != 0)) {
       uart_puts("\n\nRunning DRAM Adjustment due the system frequency changes .. ");
       em8600_mem_test(start, end, w_delay, def_freq, 1, dunit_changed);
       uart_puts("\n\n");
    }
    return(0);
}

#endif /* !CONFIG_SPECIAL_MODE */