timer.c

em86xx 完整启动程序,支持网络下载与串通下载

/*****************************************
 Copyright (c) 2002-2004
 Sigma Designs, Inc. All Rights Reserved
 Proprietary and Confidential
 *****************************************/

/* This file is part of the EM86XX boot loader */

#include "config.h"
#include "util.h"
#include "uart.h"
#include "hardware.h"
#include "em86xxapi.h"
#include "io.h"
#include "irqs.h"

// CPU_timer0_load
//   clock / HZ / (2 * prescale)
// CPU_timer0_ctrl
//   PS(D2-3) : prescale. 0x00 = 1, 0x01 = 16, 0x10 = 256
//   M(D6) : periodic mode
//   E(D7) : enable

#define HZ                      10

#define TICKS_PER_SEC           (em86xx_getclock() >> 1)
#define TIMER_PRESCALE          512
#define TIMER_PRESCALEBITS      9
#define TIMER_RELOAD            ((TICKS_PER_SEC / HZ) >> (TIMER_PRESCALEBITS))

#define TIMER_ENABLE            0x80    // D7
#define TIMER_PERIODIC          0x40    // D6
#define TIMER_PRESCALE_1        0x00    // D[2-3] = 00b
#define TIMER_PRESCALE_32       0x04    // D[2-3] = 01b
#define TIMER_PRESCALE_512      0x08    // D[2-3] = 10b

static volatile unsigned int g_ticks0 = 0;

#ifdef ENABLE_FIQ_TEST
static volatile unsigned int g_ticks1 = 0;
#endif

static void em86xx_timer0_irq(int irq, void *pdata)
{
    // clear the timer0 interrupt
    __raw_writel(1, REG_BASE_CPU + CPU_timer0_clr);

    ++g_ticks0;
}

#ifdef ENABLE_FIQ_TEST
static void em86xx_timer1_irq(int irq, void *pdata)
{
    em86xx_mask_fiq(irq);
    // clear the timer0 interrupt
    __raw_writel(1, REG_BASE_CPU + CPU_timer1_clr);

    ++g_ticks1;
    em86xx_unmask_fiq(irq);
}
#endif

void em86xx_setup_timer(void)
{
    g_ticks0 = 0;
#ifdef ENABLE_FIQ_TEST
    g_ticks1 = 0;
#endif

    // CPU_timer0_load register contains just 16-bits value
    // So, take cate not the value to overflow
    __raw_writel(TIMER_RELOAD, REG_BASE_CPU + CPU_timer0_load);
    __raw_writel(TIMER_ENABLE | TIMER_PERIODIC | TIMER_PRESCALE_512, REG_BASE_CPU + CPU_timer0_ctrl);
    __raw_writel(1, REG_BASE_CPU + CPU_timer0_clr);

#ifdef ENABLE_FIQ_TEST
    // CPU_timer1_load register contains just 16-bits value
    // So, take cate not the value to overflow
    __raw_writel(((TICKS_PER_SEC / (HZ * 10)) >> (TIMER_PRESCALEBITS)), REG_BASE_CPU + CPU_timer1_load);
    __raw_writel(TIMER_ENABLE | TIMER_PERIODIC | TIMER_PRESCALE_512, REG_BASE_CPU + CPU_timer1_ctrl);
   __raw_writel(1, REG_BASE_CPU + CPU_timer1_clr);
#endif

    em86xx_request_irq(IRQ_TIMER0, em86xx_timer0_irq, NULL);

#ifdef ENABLE_FIQ_TEST
    em86xx_request_fiq(IRQ_TIMER1, em86xx_timer1_irq, NULL);
#endif
}

unsigned int timer_getticks(void)
{
    return g_ticks0;
}

#ifdef ENABLE_FIQ_TEST
unsigned int timer_getticks1(void)
{
    return g_ticks1;
}
#endif

// timeout : in milisecond
int timer_timeout(unsigned int startticks, int timeout)
{
    unsigned int ticks = timer_getticks();
    
    timeout /= (1000 / HZ);

    if (timeout == 0)
        return 1;
    else if ((ticks - startticks) > timeout)
        return 1;

    return 0;
}