📄 hardware.h
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#define TDMX_ciper_aes_iv_6 (TDMX_cipher_base + 0xb8)#define TDMX_ciper_aes_iv_7 (TDMX_cipher_base + 0xbc)#define TDMX_ciper_aes_iv_8 (TDMX_cipher_base + 0xc0)// IDE controller : IDE controller configuration registers#define IDECTRL_base 0#if 0#define IDECTRL_idesrc (IDECTRL_base + (0x0834 << 2))#define IDECTRL_pri_drv1udmatim1 (IDECTRL_base + (0x0838 << 2))#define IDECTRL_pri_drv1udmatim2 (IDECTRL_base + (0x083c << 2))#define IDECTRL_pri_idectl (IDECTRL_base + (0x0840 << 2))#define IDECTRL_pri_drv0tim (IDECTRL_base + (0x0844 << 2))#define IDECTRL_pri_drv1tim (IDECTRL_base + (0x0848 << 2))#define IDECTRL_idemisc (IDECTRL_base + (0x084c << 2))#define IDECTRL_idestatus (IDECTRL_base + (0x0850 << 2))#define IDECTRL_udmactl (IDECTRL_base + (0x0854 << 2))#define IDECTRL_pri_drv0udmatim1 (IDECTRL_base + (0x0858 << 2))#define IDECTRL_pri_drv0udmatim2 (IDECTRL_base + (0x085c << 2))#define IDECTRL_pref_st (IDECTRL_base + (0x08c4 << 2))#endif// IDE controller : IDE device registers#if 0#define IDECTRL_pri_ctrlblock (IDECTRL_base + (0x08e6 << 2))#define IDECTRL_pri_cmdblock (IDECTRL_base + (0x08f0 << 2))#endif// IDE controller : IDE DMA channel registers#if 0#define IDECTRL_bmic (IDECTRL_base + (0x0900 << 2))#define IDECTRL_bmis (IDECTRL_base + (0x0904 << 2))#define IDECTRL_bmidtp (IDECTRL_base + (0x0908 << 2))#define IDECTRL_ide_dmaptr (IDECTRL_base + (0x09e0 << 2))#define IDECTRL_ide_dmalen (IDECTRL_base + (0x09e4 << 2))#define IDECTRL_pio_prefetch_data (IDECTRL_base + (0x09f0 << 2))#endif#define REG_BASE_HOST_BMIDE (REG_BASE_HOST + IDECTRL_pri_cmdblock)#define REG_BASE_HOST_BMIDE_DMA (REG_BASE_HOST + IDECTRL_bmic)#endif/* * DRAM Controllers * * Base Address : REG_BASE_DRAMCTRLx */// DRAM unit configuration#define DRAM_dunit_base 0x0000#if 0#define DRAM_dunit_cfg (DRAM_dunit_base + 0x00)#define DRAM_dunit_delay0_ctrl (DRAM_dunit_base + 0x04)#define DRAM_dunit_delay1_ctrl (DRAM_dunit_base + 0x08)#define DRAM_dunit_auto_delay_ctrl (DRAM_dunit_base + 0x0c)#define DRAM_dunit_delay_probe (DRAM_dunit_base + 0x10)#define DRAM_dunit_effective_delay (DRAM_dunit_base + 0x14)#define DRAM_dunit_bw_probe_cfg (DRAM_dunit_base + 0x20)#define DRAM_dunit_bw_probe_cnt (DRAM_dunit_base + 0x24)#define DRAM_dunit_flush_buffer (DRAM_dunit_base + 0x104)#endif#if 0// MBUS unit configuration#define DRAM_mbus_base 0x0200#define DRAM_mbus_w0_cfg (DRAM_mbus_base + 0x00)#define DRAM_mbus_w1_cfg (DRAM_mbus_base + 0x04)#define DRAM_mbus_w2_cfg (DRAM_mbus_base + 0x08)#define DRAM_mbus_w3_cfg (DRAM_mbus_base + 0x0c)#define DRAM_mbus_w4_cfg (DRAM_mbus_base + 0x10)#define DRAM_mbus_w5_cfg (DRAM_mbus_base + 0x14)#define DRAM_mbus_w6_cfg (DRAM_mbus_base + 0x18)#define DRAM_mbus_r0_cfg (DRAM_mbus_base + 0x40)#define DRAM_mbus_r1_cfg (DRAM_mbus_base + 0x44)#define DRAM_mbus_r2_cfg (DRAM_mbus_base + 0x48)#define DRAM_mbus_r3_cfg (DRAM_mbus_base + 0x4c)#define DRAM_mbus_r4_cfg (DRAM_mbus_base + 0x50)#define DRAM_mbus_r5_cfg (DRAM_mbus_base + 0x54)#define DRAM_mbus_r6_cfg (DRAM_mbus_base + 0x58)#define DRAM_mbus_r7_cfg (DRAM_mbus_base + 0x5c)#define DRAM_mbus_r8_cfg (DRAM_mbus_base + 0x60)#define DRAM_mbus_r9_cfg (DRAM_mbus_base + 0x64)// VBUS unit configuration#define DRAM_vbus_base 0x0300#define DRAM_vbus_r0_cfg (DRAM_vbus_base + 0x00)#define DRAM_vbus_r1_cfg (DRAM_vbus_base + 0x04)#define DRAM_vbus_r2_cfg (DRAM_vbus_base + 0x08)#define DRAM_vbus_r3_cfg (DRAM_vbus_base + 0x0c)#define DRAM_vbus_r4_cfg (DRAM_vbus_base + 0x10)#define DRAM_vbus_r5_cfg (DRAM_vbus_base + 0x14)#define DRAM_vbus_r6_cfg (DRAM_vbus_base + 0x18)#define DRAM_vbus_r7_cfg (DRAM_vbus_base + 0x1c)#endif// GBUS to LBUS bridge#define DRAM_g2l_base 0xff00#define DRAM_g2l_bist_busy (DRAM_g2l_base + 0xe0)#define DRAM_g2l_bist_pass (DRAM_g2l_base + 0xe4)#define DRAM_g2l_bist_mask (DRAM_g2l_base + 0xe8)#define DRAM_g2l_reset_control (DRAM_g2l_base + 0xfc)/* * CPU Block * * Base Address : REG_BASE_CPU */// CPU local ram#define CPU_localmem_base 0x0000 // UART - UART 0#define CPU_uart0_base 0xc100#define CPU_uart0_rxd (CPU_uart0_base + 0x00)#define CPU_uart0_txd (CPU_uart0_base + 0x04)#define CPU_uart0_inten (CPU_uart0_base + 0x08)#define CPU_uart0_intid (CPU_uart0_base + 0x0c)#define CPU_uart0_fifoctl (CPU_uart0_base + 0x10)#define CPU_uart0_linectl (CPU_uart0_base + 0x14)#define CPU_uart0_modemctl (CPU_uart0_base + 0x18)#define CPU_uart0_linestat (CPU_uart0_base + 0x1c)#define CPU_uart0_modemstat (CPU_uart0_base + 0x20)#define CPU_uart0_scratch (CPU_uart0_base + 0x24)#define CPU_uart0_clkdiv (CPU_uart0_base + 0x28)#define CPU_uart0_clkset (CPU_uart0_base + 0x2c)#define CPU_UART0_BASE (REG_BASE_CPU + CPU_uart0_base) /* UART 0 */// UART - UART 1#define CPU_uart1_base 0xc200#define CPU_uart1_rxd (CPU_uart1_base + 0x00)#define CPU_uart1_txd (CPU_uart1_base + 0x04)#define CPU_uart1_inten (CPU_uart1_base + 0x08)#define CPU_uart1_intid (CPU_uart1_base + 0x0c)#define CPU_uart1_fifoctl (CPU_uart1_base + 0x10)#define CPU_uart1_linectl (CPU_uart1_base + 0x14)#define CPU_uart1_modemctl (CPU_uart1_base + 0x18)#define CPU_uart1_linestat (CPU_uart1_base + 0x1c)#define CPU_uart1_modemstat (CPU_uart1_base + 0x20)#define CPU_uart1_scratch (CPU_uart1_base + 0x24)#define CPU_uart1_clkdiv (CPU_uart1_base + 0x28)#define CPU_uart1_clkset (CPU_uart1_base + 0x2c)#define CPU_UART1_BASE (REG_BASE_CPU + CPU_uart1_base) /* UART 0 */// Timer - Timer 0#define CPU_timer0_base 0xc500#define CPU_timer0_load (CPU_timer0_base + 0x00)#define CPU_timer0_value (CPU_timer0_base + 0x04)#define CPU_timer0_ctrl (CPU_timer0_base + 0x08)#define CPU_timer0_clr (CPU_timer0_base + 0x0c)#define CPU_TIMER0_BASE (REG_BASE_CPU + CPU_timer0_base) /* TIMER 0 */// Timer - Timer 1#define CPU_timer1_base 0xc600#define CPU_timer1_load (CPU_timer1_base + 0x00)#define CPU_timer1_value (CPU_timer1_base + 0x04)#define CPU_timer1_ctrl (CPU_timer1_base + 0x08)#define CPU_timer1_clr (CPU_timer1_base + 0x0c)#define CPU_TIMER1_BASE (REG_BASE_CPU + CPU_timer1_base) /* TIMER 1 */// Timer - RTC#define CPU_rtc_base 0xc800#if 0#define CPU_rtc_data (CPU_rtc_base + 0x00)#define CPU_rtc_match (CPU_rtc_base + 0x04)#define CPU_rtc_stat (CPU_rtc_base + 0x08)#define CPU_rtc_load (CPU_rtc_base + 0x0c)#define CPU_rtc_ctrl (CPU_rtc_base + 0x10)#endif// Interupt controller - IRQ#define CPU_irq_base 0xe000#if 0#define CPU_irq_status (CPU_irq_base + 0x00)#define CPU_irq_rawstat (CPU_irq_base + 0x04)#define CPU_irq_enableset (CPU_irq_base + 0x08)#define CPU_irq_enableclr (CPU_irq_base + 0x0c)#define CPU_irq_softset (CPU_irq_base + 0x10)#define CPU_irq_softclr (CPU_irq_base + 0x14)#endif// Interupt controller - FIQ#define CPU_fiq_base 0xe100#if 0#define CPU_fiq_status (CPU_fiq_base + 0x00)#define CPU_fiq_rawstat (CPU_fiq_base + 0x04)#define CPU_fiq_enableset (CPU_fiq_base + 0x08)#define CPU_fiq_enableclr (CPU_fiq_base + 0x0c)#define CPU_fiq_softset (CPU_fiq_base + 0x10)#define CPU_fiq_softclr (CPU_fiq_base + 0x14)#endif// Interrupt controller - Edge detector#define CPU_edge_base 0xe200#if 0#define CPU_edge_status (CPU_edge_base + 0x00)#define CPU_edge_rawstat (CPU_edge_base + 0x04)#define CPU_edge_config_rise (CPU_edge_base + 0x08)#define CPU_edge_config_fall (CPU_edge_base + 0x0c)#endif// PT110 to GBUS bridge#define CPU_remap 0xf000// RESET#define CPU_reset 0xfffc/* * Video Output * * Base Address : REG_BASE_VIDEOOUT *//* * MPEG Engine * * Base Address : REG_BASE_MPEGx *//* * Transport Demux * * Base Address : REG_BASE_TSDEMUX *//* * Audio Block * * Base Address : REG_BASE_AUDIOx *//* * Others */#define UART_NR 2 // number of UART port. // needed by drivers/char/serial_em86xx.c/* * PCI */#if defined(CONFIG_PCI_EM86XX_HOST_EM86XX) || defined(CONFIG_ENABLE_PCIHOST_EM86XX)#define PCIBIOS_MIN_IO MEMORY_BASE_PCI_IO#define PCIBIOS_MIN_MEM (MEMORY_BASE_PCI_MEMORY + 0x00100000) /* avoid 0x00000000 on bus addr */#define PCIBIOS_MIN_MEM_EM86XX (MEMORY_BASE_PCI_MEMORY + 0x10000000) /* base address of EM86xx PCI slave */#elif defined(CONFIG_PCI_EM86XX_HOST_FPGA) || defined(CONFIG_ENABLE_PCIHOST_PCIFPGA)#include <asm/arch/pcifpga.h>#define PCIBIOS_MIN_IO PCIFPGA_IO_BASE#define PCIBIOS_MIN_MEM PCIFPGA_MEMORY_BASE#endif// set to 1 if the Phy Addr == Bus Addr, otherwise 0#define PCI_DMA_BUS_IS_PHYS 1/* * Clock * * Only use timer 0 */// PLL input clock, typically 27 Mhz#define EM86XX_EXT_CLOCK 27000000 #endif⌨️ 快捷键说明
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