📄 hardware.h
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* * Base Address : REG_BASE_HOST */// Peripheral bus Registers#define HOST_pb0_base 0x0000#define HOST_pb1_base 0x0200#define HOST_pb2_base 0x0400#define HOST_pb3_base 0x0600#define HOST_pb_base_cs(n) (HOST_pb0_base + (0x0200 * (n)))// Peripheral bus CS #0 : IDE // Peripheral bus CS #1 : IDE #define PB_ide_data (PB_ide_base + IDE_data)#define PB_ide_error (PB_ide_base + IDE_error)#define PB_ide_count (PB_ide_base + IDE_count)#define PB_ide_start_sector (PB_ide_base + IDE_start_sector)#define PB_ide_cylinder_lo (PB_ide_base + IDE_cylinder_lo)#define PB_ide_cylinder_hi (PB_ide_base + IDE_cylinder_hi)#define PB_ide_head_device (PB_ide_base + IDE_head_device)#define PB_ide_cmd_stat0 (PB_ide_base + IDE_cmd_stat)#define PB_ide_irq_stat (PB_ide_base + IDE_irq_stat)#define PB_ide_cmd_stat1 (PB_ide_base + IDE_cmd_stat__)#define REG_BASE_HOST_ISAIDE (REG_BASE_HOST + PB_ide_base) // ATAPI registers// Peripheral bus configuration#define PB_cfg_base 0x0800#if 0#define PB_timing0 (PB_cfg_base + 0x00)#define PB_timing1 (PB_cfg_base + 0x04)#define PB_timing2 (PB_cfg_base + 0x08)#define PB_timing3 (PB_cfg_base + 0x0c)#define PB_timing4 (PB_cfg_base + 0x10)#define PB_timing5 (PB_cfg_base + 0x14)#endif#define PB_timing_slot(n) (PB_timing0 + (0x04 * (n)))#if 0#define PB_default_timing (PB_cfg_base + 0x18)#define PB_use_timing0 (PB_cfg_base + 0x1c)#define PB_use_timing1 (PB_cfg_base + 0x20)#define PB_use_timing2 (PB_cfg_base + 0x24)#define PB_use_timing3 (PB_cfg_base + 0x28)#define PB_use_timing4 (PB_cfg_base + 0x2c)#define PB_use_timing5 (PB_cfg_base + 0x30)#endif#define PB_use_timing_slot(n) (PB_use_timing0 + (0x04 * (n)))#define PB_cs_config (PB_CS_config)#if 0#define PB_automode_start_address (PB_cfg_base + 0x40)#define PB_automode_control (PB_cfg_base + 0x44)#endif// Switch Box #if defined(CONFIG_ARCH_MAMBO)#define SBOX_base 0x1000#define SBOX_reset (SBOX_base + 0x00)#define SBOX_route (SBOX_base + 0x04)#elif defined(CONFIG_ARCH_TANGO)#define SBOX_base 0x9000#if defined(CONFIG_ARCH_TANGO10_REV) && (CONFIG_ARCH_TANGO10_REV == 1)#define SBOX_reset (SBOX_base + 0x80)#define SBOX_route (SBOX_base + 0x88)#define SBOX_mbus_w0 (SBOX_base + 0x90)#define SBOX_mbus_w1 (SBOX_base + 0x94)#define SBOX_pci_master (SBOX_base + 0x98)#define SBOX_pci_slave (SBOX_base + 0x9c)#define SBOX_cipher (SBOX_base + 0xa0)#define SBOX_ide_isa (SBOX_base + 0xa4)#define SBOX_ide_dvd (SBOX_base + 0xa8)#else#define SBOX_reset (SBOX_base + 0xa0)#define SBOX_route (SBOX_base + 0xa8)#define SBOX_mbus_w0 (SBOX_base + 0x80)#define SBOX_mbus_w1 (SBOX_base + 0x84)#define SBOX_pci_master (SBOX_base + 0x88)#define SBOX_pci_slave (SBOX_base + 0x8c)#define SBOX_cipher (SBOX_base + 0x90)#define SBOX_ide_isa (SBOX_base + 0x94)#define SBOX_ide_dvd (SBOX_base + 0x98)#endif#endif// Semaphore#if defined(CONFIG_ARCH_TANGO)#define MISCSEM_base 0x9000#define MISC_semaphore0 (MISCSEM_base + 0x40)#define MISC_semaphore1 (MISCSEM_base + 0x44)#define MISC_semaphore2 (MISCSEM_base + 0x48)#define MISC_semaphore3 (MISCSEM_base + 0x4c)#define MISC_semaphore4 (MISCSEM_base + 0x50)#define MISC_semaphore5 (MISCSEM_base + 0x54)#define MISC_semaphore6 (MISCSEM_base + 0x58)#define MISC_semaphore7 (MISCSEM_base + 0x5c)#define MISC_semaphore8 (MISCSEM_base + 0x60)#define MISC_semaphore9 (MISCSEM_base + 0x64)#define MISC_semaphore10 (MISCSEM_base + 0x68)#define MISC_semaphore11 (MISCSEM_base + 0x6c)#define MISC_semaphore12 (MISCSEM_base + 0x70)#define MISC_semaphore13 (MISCSEM_base + 0x74)#define MISC_semaphore14 (MISCSEM_base + 0x78)#define MISC_semaphore15 (MISCSEM_base + 0x7c)#endif// Serial flash#define SFLA_base 0xa000#if 0#define SFLA_status (SFLA_base + 0x00)#define SFLA_read_parameters (SFLA_base + 0x08)#define SFLA_driver_speed (SFLA_base + 0x10)#endif#define SFLA_n_for_send_get (SFLA_base + 0x20)#if 0#define SFLA_read_data (SFLA_base + 0x30)#endif#define SFLA_send_1 (SFLA_base + 0x40)#define SFLA_send_8 (SFLA_base + 0x44)#define SFLA_send_16 (SFLA_base + 0x48)#define SFLA_send_32 (SFLA_base + 0x4c)#define SFLA_send_get_1 (SFLA_base + 0x50)#define SFLA_send_get_8 (SFLA_base + 0x54)#define SFLA_send_get_16 (SFLA_base + 0x58)#define SFLA_send_get_32 (SFLA_base + 0x5c)#define SFLA_chip_select (SFLA_base + 0x60)#define SFLA_chip_deselect (SFLA_base + 0x64)#define SFLA_send_n (SFLA_base + 0x68)#define SFLA_send_n_ (SFLA_base + 0x6c)#define SFLA_get_slaveout (SFLA_base + 0x70)#define SFLA_wait_timer (SFLA_base + 0x74)#define SFLA_send_get_n (SFLA_base + 0x78)#define SFLA_send_get_n_ (SFLA_base + 0x7c)#ifdef CONFIG_ARCH_TANGO#define SFLA_read_status (SFLA_base + 0x04)#if 0#define SFLA_drive_pads (SFLA_base + 0x0c)#endif#define SFLA_mbus_xfer_addr (SFLA_base + 0x28)#define SFLA_mbus_xfer_size (SFLA_base + 0x2c)#define SFLA_async_read_byte (SFLA_base + 0x80)#define SFLA_async_read_word (SFLA_base + 0x84)#define SFLA_async_read_dword (SFLA_base + 0x8c)#define SFLA_async_read_data (SFLA_base + 0x90)#define SFLA_async_read_size (SFLA_base + 0x94)#define SFLA_async_read_valid (SFLA_base + 0x98)#endif// MBUS interface#define MIF_w0_base MIF_W0_ADD#define MIF_w1_base MIF_W1_ADD#define MIF_r0_base MIF_R0_ADD#define MIF_r1_base MIF_R1_ADD#define MIF_add_offset 0x00#define MIF_cnt_offset 0x04#define MIF_add2_skip_offset 0x08#define MIF_cmd_offset 0x0c#define MIF_w0_add (MIF_w0_base + 0x00)#define MIF_w0_cnt (MIF_w0_base + 0x04)#define MIF_w0_add2_skip (MIF_w0_base + 0x08)#define MIF_w0_cmd (MIF_w0_base + 0x0c)#define MIF_w1_add (MIF_w1_base + 0x00)#define MIF_w1_cnt (MIF_w1_base + 0x04)#define MIF_w1_add2_skip (MIF_w1_base + 0x08)#define MIF_w1_cmd (MIF_w1_base + 0x0c)#define MIF_r0_add (MIF_r0_base + 0x00)#define MIF_r0_cnt (MIF_r0_base + 0x04)#define MIF_r0_add2_skip (MIF_r0_base + 0x08)#define MIF_r0_cmd (MIF_r0_base + 0x0c)#define MIF_r1_add (MIF_r1_base + 0x00)#define MIF_r1_cnt (MIF_r1_base + 0x04)#define MIF_r1_add2_skip (MIF_r1_base + 0x08)#define MIF_r1_cmd (MIF_r1_base + 0x0c)// PCI Timeout (slave)#define PCI_timeout_base 0x8000#define PCI_timeout_value (PCI_timeout_base + 0x00)#define PCI_timeout_status (PCI_timeout_base + 0x04)#define PCI_timer_counter (PCI_timeout_base + 0x08)#define PCI_timer_test_register (PCI_timeout_base + 0x0c)#define PCI_wakeup_register (PCI_timeout_base + 0x10)// PCI SLAVE (directly accessed, slave)#define PCI_slavecfg_base 0x9000#define PCI_region_base (PCI_slavecfg_base)#define PCI_region_0_base (PCI_region_base + 0x00)#define PCI_region_1_base (PCI_region_base + 0x04)#define PCI_region_2_base (PCI_region_base + 0x08)#define PCI_region_3_base (PCI_region_base + 0x0c)#define PCI_region_4_base (PCI_region_base + 0x10)#define PCI_region_5_base (PCI_region_base + 0x14)#define PCI_region_6_base (PCI_region_base + 0x18)#define PCI_region_7_base (PCI_region_base + 0x1c)#define PCI_slavecfg_irq (PCI_slavecfg_base + 0x20)// PCI host#if defined(CONFIG_ARCH_MAMBO)#define PCI_chip_is_host 0xe000#elif defined(CONFIG_ARCH_TANGO)#define PCI_chip_is_host 0xfe90#endif// PCI device configuration#define PCI_devcfg_base 0xfe00#define PCI_devcfg_reg0 (PCI_REG0)#define PCI_devcfg_reg1 (PCI_REG1)#define PCI_devcfg_reg2 (PCI_REG2)#define PCI_devcfg_reg3 (PCI_REG3)#define PCI_devcfg_config (PCI_CONFIG)#if (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV >= 2)) || defined(CONFIG_ARCH_TANGO)#define PCI_pcictrl_base 0xfe00#if 0#define PCI_pcictrl_reg1 (PCI_pcictrl_base + 0x88)#define PCI_pcictrl_reg2 (PCI_pcictrl_base + 0x8c)#define PCI_pcictrl_reg3 (PCI_pcictrl_base + 0xfc)#endif#endif// PCI master access#define PCI_master_base 0xfe00#define PCI_master_read_addr (PCI_master_base + 0xc0)#define PCI_master_read_counter (PCI_master_base + 0xc4)#define PCI_master_read_enable (PCI_master_base + 0xc8)#define PCI_master_read_reverse (PCI_master_base + 0xcc)#define PCI_master_write_addr (PCI_master_base + 0xd8)#define PCI_master_write_counter (PCI_master_base + 0xdc)#define PCI_master_write_enable (PCI_master_base + 0xe0)#define PCI_master_burst (PCI_master_base + 0xe4)// PCI host functionality#define PCI_host_base 0xfe00#define PCI_host_host_reg1 (PCI_host_base + 0xd0)#define PCI_host_host_reg2 (PCI_host_base + 0xd4)#define PCI_host_host_reg3 (PCI_host_base + 0x80)#define PCI_host_host_reg4 (PCI_host_base + 0x84)#ifdef CONFIG_ARCH_TANGO// Host Cipher : DES#define TDMX_cipher_base 0x5000#define TDMX_ciper_des_key_1_1 (TDMX_cipher_base + 0x00)#define TDMX_ciper_des_key_1_2 (TDMX_cipher_base + 0x04)#define TDMX_ciper_des_key_2_1 (TDMX_cipher_base + 0x08)#define TDMX_ciper_des_key_2_2 (TDMX_cipher_base + 0x0c)#define TDMX_ciper_des_key_3_1 (TDMX_cipher_base + 0x10)#define TDMX_ciper_des_key_3_2 (TDMX_cipher_base + 0x14)#define TDMX_ciper_des_iv_1 (TDMX_cipher_base + 0x18)#define TDMX_ciper_des_iv_2 (TDMX_cipher_base + 0x1c)#define TDMX_ciper_des_flags (TDMX_cipher_base + 0x20)// Host Cipher : AES#define TDMX_ciper_aes_key_1 (TDMX_cipher_base + 0x80)#define TDMX_ciper_aes_key_2 (TDMX_cipher_base + 0x84)#define TDMX_ciper_aes_key_3 (TDMX_cipher_base + 0x88)#define TDMX_ciper_aes_key_4 (TDMX_cipher_base + 0x8c)#define TDMX_ciper_aes_key_5 (TDMX_cipher_base + 0x90)#define TDMX_ciper_aes_key_6 (TDMX_cipher_base + 0x94)#define TDMX_ciper_aes_key_7 (TDMX_cipher_base + 0x98)#define TDMX_ciper_aes_key_8 (TDMX_cipher_base + 0x9c)#define TDMX_ciper_aes_aes_flags (TDMX_cipher_base + 0xa0)#define TDMX_ciper_aes_iv_1 (TDMX_cipher_base + 0xa4)#define TDMX_ciper_aes_iv_2 (TDMX_cipher_base + 0xa8)#define TDMX_ciper_aes_iv_3 (TDMX_cipher_base + 0xac)#define TDMX_ciper_aes_iv_4 (TDMX_cipher_base + 0xb0)#define TDMX_ciper_aes_iv_5 (TDMX_cipher_base + 0xb4)⌨️ 快捷键说明
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