hardware.h

em86xx 完整启动程序,支持网络下载与串通下载

/*
 * include/asm-arm/arch-em86xx/hardware.h
 *
 * Copyright 2002-2004, Sigma Designs, Inc 
 *
 * This file contains the hardware definitions for EM86XX
 *
 * by Ho Lee 01/27/2003
 */

#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H

#include "version.h"
#include "emhwlib_registers.h"
#include "board/hardware.h"

/* macro to get at IO space when running virtually */
/*  but we are not here... */
#define IO_ADDRESS(x) (x)

/* ------------------------------------------------------------------------
 *  EM86XX Memory Map as PCI Slave : relative to PCI base address
 * ------------------------------------------------------------------------
 */

// DMA Access
#if (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV == 1))
#define EM86XX_PCI_SLAVEDMA_1BYTE_BASE      0x00000000
#define EM86XX_PCI_SLAVEDMA_2BYTE_BASE      0x00001000
#define EM86XX_PCI_SLAVEDMA_3BYTE_BASE      0x00002000
#define EM86XX_PCI_SLAVEDMA_4BYTE_BASE      0x00003000
#define EM86XX_PCI_SLAVEDMA_1BYTE_REV_BASE  0x00004000
#define EM86XX_PCI_SLAVEDMA_2BYTE_REV_BASE  0x00005000
#define EM86XX_PCI_SLAVEDMA_3BYTE_REV_BASE  0x00006000
#define EM86XX_PCI_SLAVEDMA_4BYTE_REV_BASE  0x00007000
#elif (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV >= 2)) || defined(CONFIG_ARCH_TANGO)
#define EM86XX_PCI_SLAVEDMA_4BYTE_BASE      0x00000000
#define EM86XX_PCI_SLAVEDMA_4BYTE_REV_BASE  0x00004000
#endif

// Tiemout
#if (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV == 1))
#define EM86XX_PCI_TIMEOUT_VALUE            0x00008000
#define EM86XX_PCI_TIMEOUT_STATUS           0x00008004
#define EM86XX_PCI_TIMER_COUNTER            0x00008008
#define EM86XX_PCI_TIMER_TEST_REGISTER      0x0000800c
#define EM86XX_PCI_WAKEUP_REGISTER          0x00008010
#elif (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV >= 2)) || defined(CONFIG_ARCH_TANGO)
#define EM86XX_PCI_SLAVEABORT_VALUE         0x00008000
#define EM86XX_PCI_SLAVEABORT_STATUS        0x00008004
#define EM86XX_PCI_SLAVEABORT_CLEAR         0x0000800c
#define EM86XX_PCI_WAKEUP_REGISTER          0x00008010
#endif

// Slave configuration
#if 0
#define EM86XX_PCI_SLAVECFG_BASE            0x00009000
#define EM86XX_PCI_REGION_0_BASE            0x00009000
#define EM86XX_PCI_REGION_1_BASE            0x00009004
#define EM86XX_PCI_REGION_2_BASE            0x00009008
#define EM86XX_PCI_REGION_3_BASE            0x0000900c
#define EM86XX_PCI_REGION_4_BASE            0x00009010
#define EM86XX_PCI_REGION_5_BASE            0x00009014
#define EM86XX_PCI_REGION_6_BASE            0x00009018
#define EM86XX_PCI_REGION_7_BASE            0x0000901c
#define EM86XX_PCI_PCI_IRQ                  0x00009020
#else
#define EM86XX_PCI_SLAVECFG_BASE            PCI_REGION_0_BASE
#define EM86XX_PCI_REGION_0_BASE            PCI_REGION_0_BASE
#define EM86XX_PCI_REGION_1_BASE            PCI_REGION_1_BASE
#define EM86XX_PCI_REGION_2_BASE            PCI_REGION_2_BASE
#define EM86XX_PCI_REGION_3_BASE            PCI_REGION_3_BASE
#define EM86XX_PCI_REGION_4_BASE            PCI_REGION_4_BASE
#define EM86XX_PCI_REGION_5_BASE            PCI_REGION_5_BASE
#define EM86XX_PCI_REGION_6_BASE            PCI_REGION_6_BASE
#define EM86XX_PCI_REGION_7_BASE            PCI_REGION_7_BASE
#define EM86XX_PCI_PCI_IRQ                  PCI_irq_status
#endif

/* ------------------------------------------------------------------------
 *  EM86XX Memory Map and Registers as Host
 * ------------------------------------------------------------------------
 */

/*
 * EM86XX Register Base Addresses
 */

// Configuration Memory
#if 0
#define MEMORY_BASE_CONFIG          0x00000000  /* configuration space */
#define REG_BASE_SYSTEM             0x00010000  /* System Block */
#define REG_BASE_HOST               0x00020000  /* Host Interface */    
#define REG_BASE_DRAMCTRL0          0x00030000  /* DRAM Controller 0 */
#define REG_BASE_DRAMCTRL1          0x00040000  /* DRAM Controller 1 */
#define REG_BASE_DRAMCTRL2          0x00050000  /* DRAM Controller 2 */
#define REG_BASE_CPU                0x00060000  /* CPU Block */
#define REG_BASE_VIDEOOUT           0x00070000  /* Video Output */
#define REG_BASE_MPEG0              0x00080000  /* MPEG Engine 0 */
#define REG_BASE_MPEG1              0x00090000  /* MPEG Engine 1 */
#define REG_BASE_TSDEMUX            0x000a0000  /* Transport Demux */
#define REG_BASE_AUDIO0             0x000c0000  /* Audio Block 0 */
#define REG_BASE_AUDIO1             0x000d0000  /* Audio Block 1 */
#else
#define REG_BASE_SYSTEM		REG_BASE_system_block
#define REG_BASE_HOST		REG_BASE_host_interface
#define REG_BASE_CPU            REG_BASE_cpu_block
#define REG_BASE_DRAMCTRL0	REG_BASE_dram_controller_0
#define REG_BASE_DRAMCTRL1	REG_BASE_dram_controller_1
#define REG_BASE_DRAMCTRL2	REG_BASE_dram_controller_2
#endif

// RISC Memories
#if 0
#define MEMORY_BASE_RISC            0x00100000
#define REG_BASE_MPEG0_RISC         0x00100000  /* MPEG Engine 0 RISC */
#define REG_BASE_MPEG1_RISC         0x00120000  /* MPEG Engine 1 RISC */
#define REG_BASE_TSDEMUX_RISC       0x00140000  /* Transport Demux RISC */
#define REG_BASE_AUDIO0_DSP         0x00180000  /* Audio Block 0 DSP */
#define REG_BASE_AUDIO1_DSP         0x001a0000  /* Audio Block 1 DSP */
#else
#define MEMORY_BASE_RISC            MEM_BASE_mpeg_engine_0
#define REG_BASE_MPEG0_RISC         MEM_BASE_mpeg_engine_0
#define REG_BASE_MPEG1_RISC         MEM_BASE_mpeg_engine_1
#endif

// DRAM Memories
#define MEMORY_BASE_DRAMCTRL0_NC    MEM_BASE_dram_controller_0
#define MEMORY_BASE_DRAMCTRL1_NC    MEM_BASE_dram_controller_1
#define MEMORY_BASE_DRAMCTRL2_NC    MEM_BASE_dram_controller_2

#define EM86XX_DRAM_C2NC(x)         ((x) & 0x7fffffff)
#define EM86XX_DRAM_NC2C(x)         ((x) | 0x80000000)

#if 0
#if (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV == 1))
#define MEMORY_BASE_DRAMCTRL0       0x10000000  /* Memory controlled by DRAM controller 0 */
#define MEMORY_BASE_DRAMCTRL1       0x20000000  /* Memory controlled by DRAM controller 1 */
#define MEMORY_BASE_DRAMCTRL2       0x30000000  /* Memory controlled by DRAM controller 2 */
#elif (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV >= 2)) || defined(CONFIG_ARCH_TANGO)
#define MEMORY_BASE_DRAMCTRL0       0x90000000  /* Memory controlled by DRAM controller 0 */
#define MEMORY_BASE_DRAMCTRL1       0xa0000000  /* Memory controlled by DRAM controller 1 */
#define MEMORY_BASE_DRAMCTRL2       0xb0000000  /* Memory controlled by DRAM controller 2 */
#endif
#else
#if (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV == 1))
#define MEMORY_BASE_DRAMCTRL0       MEMORY_BASE_DRAMCTRL0_NC
#define MEMORY_BASE_DRAMCTRL1       MEMORY_BASE_DRAMCTRL1_NC
#define MEMORY_BASE_DRAMCTRL2       MEMORY_BASE_DRAMCTRL2_NC
#elif (defined(CONFIG_ARCH_MAMBO) && (CONFIG_ARCH_MAMBO_REV >= 2)) || defined(CONFIG_ARCH_TANGO)
#define MEMORY_BASE_DRAMCTRL0       EM86XX_DRAM_NC2C(MEMORY_BASE_DRAMCTRL0_NC)
#define MEMORY_BASE_DRAMCTRL1       EM86XX_DRAM_NC2C(MEMORY_BASE_DRAMCTRL1_NC)
#define MEMORY_BASE_DRAMCTRL2       EM86XX_DRAM_NC2C(MEMORY_BASE_DRAMCTRL2_NC)
#endif
#endif

// Host Memories
#if 0
#define MEMROY_BASE_HOST            0x40000000  /* Host memory */
#else
#define MEMROY_BASE_HOST	MEM_BASE_host_interface
#endif
#define MEMORY_BASE_HOST_SFLASH     0x40000000  /* Serial Flash */
#define MEMORY_BASE_HOST_PB0        0x44000000  /* Peripheral Bus CS #0 Memory */
#define MEMORY_BASE_HOST_PB1        0x45000000  /* Peripheral Bus CS #1 Memory */
#define MEMORY_BASE_HOST_PB2        0x46000000  /* Peripheral Bus CS #2 Memory */
#define MEMORY_BASE_HOST_PB3        0x47000000  /* Peripheral Bus CS #3 Memory */
#define MEMORY_BASE_HOST_PB_CS(n)   (MEMORY_BASE_HOST_PB0 + (0x01000000 * (n)))

// PCI Memories
#define MEMORY_BASE_PCI_CONFIG      0x50000000  /* PCI configuration */
#define MEMORY_BASE_PCI_IO          0x58000000  /* PCi I/O space */
#define MEMORY_BASE_PCI_MEMORY      0x60000000  /* PCI Memory Base */

/*
 * System Block 
 *
 * Base Address : REG_BASE_SYSTEM
 */

// Clock generator resgiers 
#define SYS_clkgen_base             0x0000
#if 0
#define SYS_clkgen0_pll             (SYS_clkgen_base + 0x00)
#define SYS_clkgen0_div             (SYS_clkgen_base + 0x04)
#define SYS_clkgen1_pll             (SYS_clkgen_base + 0x08)
#define SYS_clkgen1_div             (SYS_clkgen_base + 0x0c)
#define SYS_clkgen2_pll             (SYS_clkgen_base + 0x10)
#define SYS_clkgen2_div             (SYS_clkgen_base + 0x14)
#define SYS_clkgen3_pll             (SYS_clkgen_base + 0x18)
#define SYS_clkgen3_div             (SYS_clkgen_base + 0x1c)

#define SYS_avclk_mux               (SYS_clkgen_base + 0x38)
#define SYS_sysclk_mux              (SYS_clkgen_base + 0x3c)
#endif

// Clock cycle counters 
#if 0
#define SYS_clk_cnt                 (SYS_clkgen_base + 0x40)
#define SYS_xtal_in_cnt             (SYS_clkgen_base + 0x48)
#define SYS_vcvo0_cnt               (SYS_clkgen_base + 0x50)
#define SYS_vcxo1_cnt               (SYS_clkgen_base + 0x58)
#define SYS_rclk_out_cnt            (SYS_clkgen_base + 0x60)
#define SYS_sel_clk_cnt             (SYS_clkgen_base + 0x6c)
#endif

// MBUS arbiter 
#define MARB_base                   0x0200
#if 0
#define MARB_mid01_cfg              (MARB_base + 0x00)
#define MARB_mid21_cfg              (MARB_base + 0x04)
#define MARB_mid02_cfg              (MARB_base + 0x08)
#define MARB_mid22_cfg              (MARB_base + 0x0c)
#define MARB_mid04_cfg              (MARB_base + 0x10)
#define MARB_mid24_cfg              (MARB_base + 0x14)
#define MARB_mid25_cfg              (MARB_base + 0x18)
#define MARB_mid08_cfg              (MARB_base + 0x1c)
#define MARB_mid28_cfg              (MARB_base + 0x20)
#define MARB_mid29_cfg              (MARB_base + 0x24)
#define MARB_mid0c_cfg              (MARB_base + 0x28)
#define MARB_mid2c_cfg              (MARB_base + 0x2c)
#define MARB_mid10_cfg              (MARB_base + 0x30)
#define MARB_mid30_cfg              (MARB_base + 0x34)
#define MARB_mid31_cfg              (MARB_base + 0x38)
#define MARB_mid12_cfg              (MARB_base + 0x3c)
#define MARB_mid32_cfg              (MARB_base + 0x40)
#endif

// VBUS arbiter 
#define VARB_base                   0x0300
#if 0
#define VARB_mid01_cfg              (VARB_base + 0x00)
#define VARB_mid02_cfg              (VARB_base + 0x04)
#define VARB_mid21_cfg              (VARB_base + 0x08)
#define VARB_mid22_cfg              (VARB_base + 0x0c)
#define VARB_mid23_cfg              (VARB_base + 0x10)
#define VARB_mid24_cfg              (VARB_base + 0x14)
#define VARB_mid25_cfg              (VARB_base + 0x18)
#define VARB_mid26_cfg              (VARB_base + 0x1c)
#define VARB_mid27_cfg              (VARB_base + 0x20)
#define VARB_mid28_cfg              (VARB_base + 0x24)
#define VARB_mid29_cfg              (VARB_base + 0x28)
#define VARB_mid2a_cfg              (VARB_base + 0x2c)
#define VARB_mid10_cfg              (VARB_base + 0x30)
#define VARB_mid30_cfg              (VARB_base + 0x34)
#define VARB_mid31_cfg              (VARB_base + 0x38)
#endif

// IBUS arbiter
#define IARB_base                   0x0400
#if 0
#define IARB_mid01_cfg              (IARB_base + 0x00)
#define IARB_mid02_cfg              (IARB_base + 0x04)
#endif

// GPIO 
#define SYS_gpio_base               0x0500
#if 0
#define SYS_gpio_dir                (SYS_gpio_base + 0x00)
#define SYS_gpio_data               (SYS_gpio_base + 0x04)
#define SYS_gpio_irq                (SYS_gpio_base + 0x08)
#define SYS_gpio15_pwm              (SYS_gpio_base + 0x10)
#define SYS_gpio14_pwm              (SYS_gpio_base + 0x14)
#endif

#define GPIO_DIR_INPUT(gpio)        ((1 << (16 + (gpio))))
#define GPIO_DIR_OUTPUT(gpio)       ((1 << (16 + (gpio))) | (1 << (gpio)))
#define GPIO_DATA_SET(gpio)         ((1 << (16 + (gpio))) | (1 << (gpio)))
#define GPIO_DATA_CLEAR(gpio)       ((1 << (16 + (gpio))))

/*
 * Host Interface