pcicommon.h

em86xx 完整启动程序,支持网络下载与串通下载

/*****************************************
 Copyright (c) 2003-2004
 Sigma Designs, Inc. All Rights Reserved
 Proprietary and Confidential
 *****************************************/

/* This file is part of the EM86XX boot loader */

/*
 * pcicommon.h
 *
 * by Ho Lee 02/05/2003
 */

#ifndef __BOOTLOADER_PCICOMMON_H
#define __BOOTLOADER_PCICOMMON_H

//
// PCI definitions : configuration
// 

#define PCI_VENDOR_ID               0x00    /* 16 bits */
#define PCI_DEVICE_ID               0x02    /* 16 bits */
#define PCI_COMMAND                 0x04    /* 16 bits */
#define  PCI_COMMAND_IO             0x1     /* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY         0x2     /* Enable response in Memory space */
#define  PCI_COMMAND_MASTER         0x4     /* Enable bus mastering */
#define PCI_STATUS                  0x06    /* 16 bits */
#define PCI_CLASS_REVISION          0x08    /* High 24 bits are class, low 8 revision */
#define  PCI_CLASS_BRIDGE_PCI       0x0604
#define PCI_CACHE_LINE_SIZE         0x0c    /* 8 bits */
#define PCI_LATENCY_TIMER           0x0d    /* 8 bits */
#define PCI_HEADER_TYPE             0x0e    /* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL     0
#define  PCI_HEADER_TYPE_BRIDGE     1
#define  PCI_HEADER_TYPE_CARDBUS    2
#define PCI_BASE_ADDRESS_0          0x10    /* 32 bits */
#define PCI_BASE_ADDRESS_1          0x14    /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2          0x18    /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3          0x1c    /* 32 bits */
#define PCI_BASE_ADDRESS_4          0x20    /* 32 bits */
#define PCI_BASE_ADDRESS_5          0x24    /* 32 bits */
#define  PCI_BASE_ADDRESS_SPACE     0x01    /* 0 = memory, 1 = I/O */
#define  PCI_BASE_ADDRESS_SPACE_IO  0x01
#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
#define  PCI_BASE_ADDRESS_MEM_MASK  (~0x0fUL)
#define  PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)
#define PCI_ROM_ADDRESS             0x30    /* Bits 31..11 are address, 10..1 reserved */
#define PCI_INTERRUPT_LINE          0x3c    /* 8 bits */
#define PCI_INTERRUPT_PIN           0x3d    /* 8 bits */

#define PCI_PRIMARY_BUS             0x18    /* Primary bus number */
#define PCI_SECONDARY_BUS           0x19    /* Secondary bus number */
#define PCI_SUBORDINATE_BUS         0x1a    /* Highest bus number behind the bridge */

//
// PCI signal definitions
// 

#define PCI_CMD_IOREAD              0x02
#define PCI_CMD_IOWRITE             0x03
#define PCI_CMD_MEMORYREAD          0x06
#define PCI_CMD_MEMORYWRITE         0x07
#define PCI_CMD_CONFIGREAD          0x0a
#define PCI_CMD_CONFIGWRITE         0x0b

//
// PCI data structure
//

struct my_pci_dev {
    int idsel;
    int is_normal, is_bridge, is_cardbus;
    
    unsigned int vendor_id, device_id;
    unsigned int cmd, status, class, rev; 
    unsigned int progIF, subclass, classcode;
    unsigned int hdr_type, latency, cacheline;

    // base_addr : read directly from PCI configuration space
    // resource : cooked base address. device driver should refer to this information
    unsigned int base_addr[6];
    struct {
        int isio;
        unsigned int start;
        unsigned int size;  
    } resource[6];
    
    // normal
    unsigned int irqpin, irqline;
    unsigned int romaddr;
    
    // bridge
    unsigned int buses;
    unsigned int primary_bus, secondary_bus, subordinate_bus;
    
    // cardbus
};

struct my_pci_op {
    // valid IDSEL range
    int idsel_start, idsel_end;
    // difference between physical address and bus address of 
    // PCI memory space and PCI I/O space respectively
    unsigned int mem_offset, io_offset;

    // basic
    int (*init)(int verbose);
    int (*info)(void);
    unsigned int (*select)(int idsel);
    unsigned int (*virt_to_bus)(unsigned int virt);
    unsigned int (*bus_to_virt)(unsigned int bus);
    unsigned int (*pciio_base)(int idsel);
    unsigned int (*pcimemory_base)(int idsel);

    // configuration space
    int (*read_config_byte)(unsigned int addr, unsigned char *data8);
    int (*read_config_word)(unsigned int addr, unsigned short *data16);
    int (*read_config_dword)(unsigned int addr, unsigned int *data32);
    int (*write_config_byte)(unsigned int addr, unsigned int data8);
    int (*write_config_word)(unsigned int addr, unsigned int data16);
    int (*write_config_dword)(unsigned int addr, unsigned int data32);

    // I/O space
    unsigned char (*in_byte)(unsigned int addr);
    unsigned short (*in_word)(unsigned int addr);
    unsigned int (*in_dword)(unsigned int addr);
    void (*out_byte)(unsigned int data, unsigned int addr);
    void (*out_word)(unsigned int data, unsigned int addr);
    void (*out_dword)(unsigned int data, unsigned int addr);
    
    // memory space
    unsigned char (*read_byte)(unsigned int addr);
    unsigned short (*read_word)(unsigned int addr);
    unsigned int (*read_dword)(unsigned int addr);
    void (*write_byte)(unsigned int data, unsigned int addr);
    void (*write_word)(unsigned int data, unsigned int addr);
    void (*write_dword)(unsigned int data, unsigned int addr);
    
    // test
    int (*test)(int argc, char *argv[]);
};

//
// global variables
//

extern struct my_pci_op *g_pciop;

//
// function prototypes
//

// init
int pci_init(struct my_pci_op *pop, int verbose);

// basic
int pci_info(void);
unsigned int pci_select(int idsel);

// bus address translation
unsigned int virt_to_bus(unsigned int virt);
unsigned int bus_to_virt(unsigned int bus);

// configuration space
int pci_read_config_byte(unsigned int addr, unsigned char *data8);
int pci_read_config_word(unsigned int addr, unsigned short *data16);
int pci_read_config_dword(unsigned int addr, unsigned int *data32);
int pci_write_config_byte(unsigned int addr, unsigned int data8);
int pci_write_config_word(unsigned int addr, unsigned int data16);
int pci_write_config_dword(unsigned int addr, unsigned int data32);

// I/O space
unsigned char pci_inb(unsigned int addr);
unsigned short pci_inw(unsigned int addr);
unsigned int pci_inl(unsigned int addr);
void pci_outb(unsigned int data, unsigned int addr);
void pci_outw(unsigned int data, unsigned int addr);
void pci_outl(unsigned int data, unsigned int addr);

// memory space
unsigned char pci_readb(unsigned int addr);
unsigned short pci_readw(unsigned int addr);
unsigned int pci_readl(unsigned int addr);
void pci_writeb(unsigned int data, unsigned int addr);
void pci_writew(unsigned int data, unsigned int addr);
void pci_writel(unsigned int data, unsigned int addr);

// PCI bus scan & dump
int pci_scan(void);
struct my_pci_dev *pci_get_info(struct my_pci_dev *pdev, int readonly);
void pci_dump(struct my_pci_dev *pdev);
void pci_dump_idsel(int idsel, int readonly);

// APIs for device drivers
struct my_pci_dev *pci_lookup(unsigned int vendor_id, unsigned int device_id, struct my_pci_dev *pdev);
struct my_pci_dev *pci_lookup_idsel(int idsel, struct my_pci_dev *pdev);
void pci_configure_device(struct my_pci_dev *pdev);

// test
int pci_test(int argc, char *argv[]);

#endif