loader-sflash-min.s

em86xx 完整启动程序,支持网络下载与串通下载

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# 26 "loader-stage0.S" 2


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# 28 "loader-stage0.S" 2

# 1 "memcfg.h" 1

 




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# 7 "memcfg.h" 2

# 1 "emhwlib_dram.h" 1
 




 








































# 69 "emhwlib_dram.h"



 
# 8 "memcfg.h" 2


# 38 "memcfg.h"



# 29 "loader-stage0.S" 2





 




 








    .text
    .code 32
    .align 0

    .global stage0_start


@
@ Serial Flash signature 4 bytes
@

    .long 0x7f02ed7e            @ BYTE 0 : signature = 0x7e (or 0x9e)
                                @ BYTE 1 : signature = 0xed
                                @ BYTE 2 : [6..7] signature = 0
                                @          [5] chip desect clocked = 0
                                @          [0..1] address bits = 2 (24 bits : 3 bytes_in_address - 1)
                                @ BYTE 3 : [7] A8 sent in read command = 0
                                @          [0..6] stuff bits = 0x7f


    b   stage0_start            @ offset 0x00

@
@ user configurable settings : 0x60 - 4
@

config_start:

data_filesize:                  @ offset 0x04 : stage 1 boot loader size
    .long 0x00000000
data_version:                   @ offset 0x08
 
    .long ((( 0 ) << 16) | ((  12 ) << 8) | (  17 ))  
data_signature:                 @ offset 0x0c
    .long 0x424d414d 

data_SYS_clkgen0_pll:           @ offset 0x10
                                @ FIN = 27000000  (e.g. 27000000)
                                @ clock = (FIN * (N + 2) / (M + 2)) / 2
    @ .long 0x0101002e          @ (46 + 2) / (1 + 2) = 16 : FIN * 16 / 2 = 216.0 MHz
    @ .long 0x0101002b          @ (43 + 2) / (1 + 2) = 15 : FIN * 15 / 2 = 202.5 MHz
    @ .long 0x01010028          @ (40 + 2) / (1 + 2) = 14 : FIN * 14 / 2 = 189.0 MHz
    @ .long 0x01010025          @ (37 + 2) / (1 + 2) = 13 : FIN * 13 / 2 = 175.5 MHz
    @ .long 0x01010022          @ (34 + 2) / (1 + 2) = 12 : FIN * 12 / 2 = 162.0 MHz
    @ .long 0x0101001f          @ (31 + 2) / (1 + 2) = 11 : FIN * 11 / 2 = 148.5 MHz
    @ .long 0x0101001c          @ (28 + 2) / (1 + 2) = 10 : FIN * 10 / 2 = 135.0 MHz
    @ .long 0x01010019          @ (25 + 2) / (1 + 2) = 9 : FIN * 9 / 2 = 121.5 MHz
    @ .long 0x01010016          @ (22 + 2) / (1 + 2) = 8 : FIN * 8 / 2 = 108.0 MHz
    .long 0x0101002a 
data_DRAM0_dunit_cfg:           @ offset 0x14
    @ .long 0xe34000b8
    .long 0xf63001f8 
data_DRAM1_dunit_cfg:           @ offset 0x18
    @ .long 0xe34000b8
    @ .long 0x133000bc
    @ .long 0x0
    .long 0 
data_DRAM_dunit_delay0_ctrl:    @ offset 0x1c
    .long 0x00084454 


data_SFLA_driver_speed:         @ offset 0x20
    .long 0x0f000003 







data_pci_subsystem_id:          @ offset 0x24
    .long 0x00000000 
data_pci_revision_id:           @ offset 0x28
    .long 0    @ Rev. A = 1, Rev. B = 2
data_pci_memory_size:           @ offset 0x2c
    .long 0 

data_bootflag:                  @ offset 0x30
    @.long 0x00 
    @.long (0x01  | (( 0x02  ) << 2) )
    @.long (0x01  | (( 0x01  ) << 2)  | (( 0x02  ) << 6) )
    @.long (0x01  | (( 0x03  ) << 2) )
    .long 0x00  

data_configvalid:               @ offset 0x34
    .long (1 << 0)  

data_dramsize:                  @ offset 0x38
    .long ((  5   )  | ((   0   ) << 8) ) 

data_imagesize:                 @ offset 0x3c : entire image size except serial flash signature
    .long 0x00000000
data_checksum:                  @ offset 0x40 : checksum 
    .long 0x00000000

# 157 "loader-stage0.S"


config_end:

@
@ debugging
@
@ uart_init : initialize UART 0
@ uart_putc : print out one character (debug, production test)
@ uart_putc_debug : print out one character (debug only)
@


    .equ    UART_INTEN, 0x08
    .equ    UART_FIFOCTL, 0x10
    .equ    UART_LINECTL, 0x14
    .equ    UART_CLKDIV, 0x28
    .equ    UART_CLKSEL, 0x2c

    .macro uart_init, reg1, reg2
    ldr \reg1, =(0x00060000   + 0xc100 )
    mov \reg2, #0x00            @ disable interrupt
    str \reg2, [\reg1, #UART_INTEN]
    mov \reg2, #0x1f
    str \reg2, [\reg1, #UART_FIFOCTL]
    mov \reg2, #0x03            @ N-8-1
    str \reg2, [\reg1, #UART_LINECTL]



    mov \reg2, #0x01            @ external clock

    str \reg2, [\reg1, #UART_CLKSEL]
# 200 "loader-stage0.S"


    mov \reg2, #((27000000 ) /(16* 57600 ))





    str \reg2, [\reg1, #UART_CLKDIV]
    .endm

    .macro uart_putc, ch, reg1, reg2







    ldr \reg1, =(0x00060000   + (0xc100  + 0x04) )
    mov \reg2, \ch
    str \reg2, [\reg1]
    .endm

    .macro uart_putc_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm
# 237 "loader-stage0.S"



    .macro uart_putc_debug_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm





@
@ initialize Serial Flash & PLL
@ After hard reset, CPU operates at 13.5MHz
@

stage0_start:
    @ internally use :
    @  r0, r1 : register
    @  r2 : data


    @ set serial flash speed compatible with high CPU clock
    ldr r0, =(0x00020000   + 0xa010 )
    ldr r2, data_SFLA_driver_speed
    str r2, [r0]







    @ set PLL
    ldr r1, =(0x00010000   + 0x0000 )
    ldr r2, data_SYS_clkgen0_pll
    str r2, [r1]

    @ set clock MUX
    ldr r1, =(0x00010000   + 0x003C )
    mov r2, #1
    str r2, [r1]

    @ invalidate and disable caches
    mov r0, #0x00
    mcr p15, 0x0, r0, c7, c5, 0     @ Invalidate Instruction Cache (all)
    mcr p15, 0x0, r0, c7, c6, 0     @ Invalidate Data Cache (all)
    mcr p15, 0x0, r0, c1, c0, 0     @ disable all cache

    @ setup initial fiq stack top
setup_fiq_stack:
    mrs r1, cpsr		    @ save old cpsr
    msr cpsr_c, #0xd1		    @ FIQ mode, disable IRQ/FIQ
    ldr r0, =(0x90000000  + 0x00050000 ) @ growing downward
    mov sp, r0			    @ set stack
    msr cpsr_c, r1		    @ restore old cpsr

# 350 "loader-stage0.S"










@
@ initialize DRAM
@

dram_init:

    uart_init r10, r11
    uart_putc #'D', r10, r11

    @ initialize DRAM controller 0
    uart_putc_io #'1', r10, r11
    mov r0, #0x00030000  
    ldr r1, data_DRAM0_dunit_cfg
    ldr r2, data_DRAM_dunit_delay0_ctrl
    bl dram_init_ctrl

    @ initialize DRAM controller 1
    uart_putc_io #'2', r10, r11
    mov r0, #0x00040000  
    ldr r1, data_DRAM1_dunit_cfg
    bl dram_init_ctrl

    b cache_init

dram_init_ctrl:
    @ initialize each DRAM controller
    @ call with :
    @  r0 = base address of DRAM controller register
    @  r1 = setting for 0x0000 
    @    if this setting is 0, just disable the DRAM controller
    @  r2 = setting for 0x0004 
    @ internally use :
    @  r3, r4 : register
    @  r5 : data

    @ reset
    add r3, r0, #0xff00 
    add r3, r3, #((0xff00  + 0xfc)  - 0xff00 )
    mov r5, #0x03
    strb r5, [r3]
    cmp r1, #0x00       @ if the DRAM should be disabled
    moveq pc, lr        @ just return here
    mov r5, #0x02
    strb r5, [r3]

    @ DRAM configuration
    add r4, r0, #0x0000 
    str r1, [r4]

    @ DRAM delay control
    add r4, r0, #0x0004 
    str r2, [r4]

    @ full operation
    mov r5, #0x00
    strb r5, [r3]

    @ return to caller
    mov pc, lr

@
@ cache control
@

cache_init:

    uart_putc_io #'C', r10, r11

# 461 "loader-stage0.S"


@
@ do other initialization
@

misc_init:


    @
    @ this procedure is done by em86xx_bootconfig()
    @

    @ load configvalid
    ldr r3, data_configvalid

    @ setup PCI subsystem ID
    ldr r0, =(0x00020000   + 0xfe00 )
    ldr r1, data_pci_subsystem_id
    tst r3, #(1 << 0) 
    strne r1, [r0, #((0xfef0 )  - 0xfe00 )]

    @ setup PCI revision
    ldr r1, [r0, #((0xfeec )  - 0xfe00 )]
    ldr r2, data_pci_revision_id
    bic r1, r1, #0xff
    orr r1, r1, r2
    tst r3, #(1 << 1) 
    strne r1, [r0, #((0xfeec )  - 0xfe00 )]

    @ setup PCI memory size
    ldr r1, [r0, #((0xfef4 )  - 0xfe00 )]
    ldr r2, data_pci_memory_size
    bic r1, r1, #0x07
    orr r1, r1, r2
    tst r3, #(1 << 2) 
    strne r1, [r0, #((0xfef4 )  - 0xfe00 )]

    @ set PCI configuration valid bit
    mov r1, #0x00010000
    str r1, [r0, #((0xfe00  + 0xd4)  - 0xfe00 )]

    @
    @ this procedure is done by em86xx_init()
    @

    @ setup remap register
    ldr r0, =(0x00060000   + 0xf000 )
    ldr r1, =(0x90000000 )
    str r1, [r0]

    @ setup GPIO and IRQ mapping
    ldr r0, =(0x00010000   + 0x0508 )
    ldr r1, =(0x0a090806 )
    str r1, [r0]

    @ setup peripheral bus interface
    ldr r0, =(0x00020000   + 0x0800 )
    ldr r1, =(0x10101010 )
    str r1, [r0, #(0x0818  - 0x0800 )]

    ldr r1, =(0x00001044 )
    str r1, [r0, #(0x0818  - 0x0800 )]

    @ setup timing 0 
    @ r0 is already set before
    ldr r1, =(0x10101010 )
    str r1, [r0, #(0x0800  - 0x0800 )]
    ldr r1, =(0x000001f4 )
    str r1, [r0, #(0x081c  - 0x0800 )]

    @ setup timing 1
    ldr r1, =(0x00110101 )
    str r1, [r0, #(0x0804  - 0x0800 )]
    ldr r1, =(0x000003f3 )
    str r1, [r0, #(0x0820  - 0x0800 )]

    @ setup timing 2
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0808  - 0x0800 )]
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0824  - 0x0800 )]

    @ setup timing 3
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x080c  - 0x0800 )]
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0828  - 0x0800 )]

    @ setup timing 4
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0810  - 0x0800 )]
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x082c  - 0x0800 )]

    @ setup timing 5
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0814  - 0x0800 )]
    ldr r1, =(0x00000000 )
    str r1, [r0, #(0x0830  - 0x0800 )]


@
@ DRAM adjustment
@

# 584 "loader-stage0.S"


@
@ Crypto stage 0
@

# 619 "loader-stage0.S"


@
@ production test
@

# 642 "loader-stage0.S"


@
@ load main boot loader to DRAM
@



loop:
    b loop

# 857 "loader-stage0.S"