optab-x86.dat

It s a Linux disassemble, can set break point, disassemble ELF file.

# $Id: optab-x86.dat,v 1.1.1.1 2004/04/26 00:40:21 pa33 Exp $
#
# File format:
# <Instruction> <Operands> <Opcodes> [flag]
#
# NOTE: The accompanying script "optab.pl" requires the instruction
#       names to be in alphabetical order.
#
# Possible values of the [flag] are as follows:
#
#  0 - 7   : column of modR/M table to use
#  r       : can use any column
#  c       : register code (Table 3.1 in Instruction Set Reference)
#  f       : FPU stack register code
#
# The nomenclature of this file deviates from Intel's Instruction
# Set Reference in the following ways:
#
# Intel                                 Me
# /r                                    "r" in [flag] column
# /digit                                "digit" in [flag] column
# +rb/+rw/+rd                           "c" in [flag] column
# +i                                    "f" in [flag] column
# cr0                                   r(cr0)
# cr2                                   r(cr2)
# cr3                                   r(cr3)
# cr4                                   r(cr4)
# ib                                    imm8
# iw                                    imm16
# id                                    imm32
# m16&16                                mem16
# m16&32                                mem32
# m32&32                                mem32
# m8                                    mem8
# m16                                   mem16
# m32                                   mem32
# m64                                   mem64
# m80                                   mem80
# m16:16                                rm16
# m16:32                                rm32
# mm                                    mmxreg
# mm1                                   mmxreg
# mm/m64                                mem64
# moffs{8,16,32}                        moffs
# ptr16:16                              ptr16:16
# ptr16:32                              ptr16:32
# Sreg                                  segreg
# st(0)                                 r(st0)
# st(i)                                 fpureg
# xmm                                   xmmreg
# xmm1                                  xmmreg
# xmm?/m*                               mem128
# r32 (using rm field)                  reg32_rm
#
# no operands                           void
# no operands/32 bit addressing         void32
# numerical constant (ie: 1)            const<number>
#
# For opcodes which require specific registers (ie: al,ax etc)
# I will use the syntax: r##(register). Where ## is an optional
# size of the register. So, for al, it would be: r8(al)
#
# The rest of the nomenclature of this file is mostly identical to
# that of intel.

AAA       void                37

AAD       void                D5,0A
AAD       imm8                D5

AAM       void                D4,0A
AAM       imm8                D4

AAS       void                3F

ADC       r8(al),imm8         14
ADC       r16(ax),imm16       15
ADC       r32(eax),imm32      15
ADC       rm8,imm8            80                 2
ADC       rm16,imm16          81                 2
ADC       rm32,imm32          81                 2
ADC       rm16,imm8           83                 2
ADC       rm32,imm8           83                 2
ADC       rm8,reg8            10                 r
ADC       rm16,reg16          11                 r
ADC       rm32,reg32          11                 r
ADC       reg8,rm8            12                 r
ADC       reg16,rm16          13                 r
ADC       reg32,rm32          13                 r

ADD       r8(al),imm8         04
ADD       r16(ax),imm16       05
ADD       r32(eax),imm32      05
ADD       rm8,imm8            80                 0
ADD       rm16,imm16          81                 0
ADD       rm32,imm32          81                 0
ADD       rm16,imm8           83                 0
ADD       rm32,imm8           83                 0
ADD       rm8,reg8            00                 r
ADD       rm16,reg16          01                 r
ADD       rm32,reg32          01                 r
ADD       reg8,rm8            02                 r
ADD       reg16,rm16          03                 r
ADD       reg32,rm32          03                 r

ADDPS     xmmreg,mem128       0F,58              r

AND       r8(al),imm8         24
AND       r16(ax),imm16       25
AND       r32(eax),imm32      25
AND       rm8,imm8            80                 4
AND       rm16,imm16          81                 4
AND       rm32,imm32          81                 4
AND       rm16,imm8           83                 4
AND       rm32,imm8           83                 4
AND       rm8,reg8            20                 r
AND       rm16,reg16          21                 r
AND       rm32,reg32          21                 r
AND       reg8,rm8            22                 r
AND       reg16,rm16          23                 r
AND       reg32,rm32          23                 r

ARPL      rm16,reg16          63                 r

BOUND     reg16,mem16         62                 r
BOUND     reg32,mem32         62                 r

BSF       reg16,rm16          0F,BC              r
BSF       reg32,rm32          0F,BC              r

BSR       reg16,rm16          0F,BD              r
BSR       reg32,rm32          0F,BD              r

BSWAP     reg32               0F,C8              c

BT        rm16,reg16          0F,A3              r
BT        rm32,reg32          0F,A3              r
BT        rm16,imm8           0F,BA              4
BT        rm32,imm8           0F,BA              4

BTC       rm16,reg16          0F,BB              r
BTC       rm32,reg32          0F,BB              r
BTC       rm16,imm8           0F,BA              7
BTC       rm32,imm8           0F,BA              7

BTR       rm16,reg16          0F,B3              r
BTR       rm32,reg32          0F,B3              r
BTR       rm16,imm8           0F,BA              6
BTR       rm32,imm8           0F,BA              6

BTS       rm16,reg16          0F,AB              r
BTS       rm32,reg32          0F,AB              r
BTS       rm16,imm8           0F,BA              5
BTS       rm32,imm8           0F,BA              5

CALL      rel16|near          E8
CALL      rel32|near          E8
CALL      rm16|near           FF                 2
CALL      rm32|near           FF                 2
CALL      ptr16:16|far        9A
CALL      ptr16:32|far        9A
CALL      rm16|far            FF                 3
CALL      rm32|far            FF                 3

CBW       void                98

CDQ       void32              99

CLC       void                F8
CLD       void                FC
CLI       void                FA
CLTS      void                0F,06

CMC       void                F5

# CMOVA and CMOVNBE have the exact same opcode - we shall use
# CMOVA for this opcode.
CMOVA     reg16,rm16          0F,47              r
CMOVA     reg32,rm32          0F,47              r

# CMOVB, CMOVC, and CMOVNAE have the exact opcode - we shall use
# CMOVC for this opcode.
CMOVC     reg16,rm16          0F,42              r
CMOVC     reg32,rm32          0F,42              r

CMOVE     reg16,rm16          0F,44              r
CMOVE     reg32,rm32          0F,44              r
CMOVG     reg16,rm16          0F,4F              r
CMOVG     reg32,rm32          0F,4F              r

# CMOVL and CMOVNGE have the exact same opcode - we shall use
# CMOVL for this opcode.
CMOVL     reg16,rm16          0F,4C              r
CMOVL     reg32,rm32          0F,4C              r

# CMOVLE and CMOVNG have the exact same opcode - we shall use
# CMOVLE for this opcode.
CMOVLE    reg16,rm16          0F,4E              r
CMOVLE    reg32,rm32          0F,4E              r

# CMOVBE and CMOVNA have the exact same opcode - we shall use
# CMOVNA for this opcode.
CMOVNA    reg16,rm16          0F,46              r
CMOVNA    reg32,rm32          0F,46              r

# CMOVAE, CMOVNB, and CMOVNC have the exact same opcode - we shall
# use CMOVNC for this opcode.
CMOVNC    reg16,rm16          0F,43              r
CMOVNC    reg32,rm32          0F,43              r

CMOVNE    reg16,rm16          0F,45              r
CMOVNE    reg32,rm32          0F,45              r

# CMOVGE and CMOVNL have the exact same opcode - we shall use
# CMOVNL for this opcode.
CMOVNL    reg16,rm16          0F,4D              r
CMOVNL    reg32,rm32          0F,4D              r

CMOVNO    reg16,rm32          0F,41              r
CMOVNO    reg32,rm32          0F,41              r
CMOVNP    reg16,rm16          0F,4B              r
CMOVNP    reg32,rm32          0F,4B              r
CMOVNS    reg16,rm16          0F,49              r
CMOVNS    reg32,rm32          0F,49              r
CMOVO     reg16,rm16          0F,40              r
CMOVO     reg32,rm32          0F,40              r
CMOVP     reg16,rm32          0F,4A              r
CMOVP     reg32,rm32          0F,4A              r
CMOVS     reg16,rm16          0F,48              r
CMOVS     reg32,rm32          0F,48              r

CMP       r8(al),imm8         3C
CMP       r16(ax),imm16       3D
CMP       r32(eax),imm32      3D
CMP       rm8,imm8            80                 7
CMP       rm16,imm16          81                 7
CMP       rm32,imm32          81                 7
CMP       rm16,imm8           83                 7
CMP       rm32,imm8           83                 7
CMP       rm8,reg8            38                 r
CMP       rm16,reg16          39                 r
CMP       rm32,reg32          39                 r
CMP       reg8,rm8            3A                 r
CMP       reg16,rm16          3B                 r
CMP       reg32,rm32          3B                 r

CMPSB     void                A6
CMPSD     void32              A7
CMPSW     void                A7

CMPXCHG   rm8,reg8            0F,B0              r
CMPXCHG   rm16,reg16          0F,B1              r
CMPXCHG   rm32,reg32          0F,B1              r
CMPXCHG8B mem64               0F,C7              1

CPUID     void                0F,A2

CWD       void                99

CWDE      void32              98

DAA       void                27

DAS       void                2F

DEC       rm8                 FE                 1
DEC       rm16                FF                 1
DEC       rm32                FF                 1
DEC       reg16               48                 c
DEC       reg32               48                 c

DIV       rm8                 F6                 6
DIV       rm16                F7                 6
DIV       rm32                F7                 6

EMMS      void                0F,77

ENTER     imm16,imm8          C8

F2XM1     void                D9,F0

FABS      void                D9,E1

FADD      r(st0),mem32        D8                 0
FADD      r(st0),mem64        DC                 0
FADD      r(st0),fpureg       D8,C0              f
FADD      fpureg,r(st0)       DC,C0              f
FADDP     fpureg,r(st0)       DE,C0              f

FBLD      r(st0),mem80        DF                 4

FBSTP     mem80,r(st0)        DF                 6

FCHS      r(st0)              D9,E0

FCLEX     void                9B,DB,E2

FCMOVB    r(st0),fpureg       DA,C0              f
FCMOVBE   r(st0),fpureg       DA,D0              f
FCMOVE    r(st0),fpureg       DA,C8              f
FCMOVNB   r(st0),fpureg       DB,C0              f
FCMOVNBE  r(st0),fpureg       DB,D0              f
FCMOVNE   r(st0),fpureg       DB,C8              f
FCMOVNU   r(st0),fpureg       DB,D8              f
FCMOVU    r(st0),fpureg       DA,D8              f

FCOM      r(st0),mem32        D8                 2
FCOM      r(st0),mem64        DC                 2
FCOM      r(st0),fpureg       D8,D0              f

FCOMI     r(st0),fpureg       DB,F0              f
FCOMIP    r(st0),fpureg       DF,F0              f

FCOMP     r(st0),mem32        D8                 3
FCOMP     r(st0),mem64        DC                 3
FCOMP     r(st0),fpureg       D8,D8              f
FCOMPP    r(st1),r(st0)       DE,D9

FCOS      r(st0)              D9,FF

FDECSTP   void                D9,F6

FDIV      r(st0),mem32        D8                 6
FDIV      r(st0),mem64        DC                 6
FDIV      r(st0),fpureg       D8,F0              f
FDIV      fpureg,r(st0)       DC,F8              f
FDIVP     fpureg,r(st0)       DE,F8              f

FDIVR     r(st0),mem32        D8                 7
FDIVR     r(st0),mem64        DC                 7
FDIVR     r(st0),fpureg       D8,F8              f
FDIVR     fpureg,r(st0)       DC,F0              f
FDIVRP    fpureg,r(st0)       DE,F0              f

FFREE     fpureg              DD,C0              f

FIADD     r(st0),mem32        DA                 0
FIADD     r(st0),mem16        DE                 0

FICOM     r(st0),mem16        DE                 2
FICOM     r(st0),mem32        DA                 2
FICOMP    r(st0),mem16        DE                 3
FICOMP    r(st0),mem32        DA                 3

FIDIV     r(st0),mem32        DA                 6
FIDIV     r(st0),mem16        DE                 6

FIDIVR    r(st0),mem32        DA                 7
FIDIVR    r(st0),mem16        DE                 7

FILD      r(st0),mem16        DF                 0
FILD      r(st0),mem32        DB                 0
FILD      r(st0),mem64        DF                 5

FIMUL     r(st0),mem32        DA                 1
FIMUL     r(st0),mem16        DE                 1

FINCSTP   void                D9,F7

FINIT     void                9B,DB,E3

FIST      mem16,r(st0)        DF                 2
FIST      mem32,r(st0)        DB                 2
FISTP     mem16,r(st0)        DF                 3
FISTP     mem32,r(st0)        DB                 3
FISTP     mem64,r(st0)        DF                 7

FISUB     r(st0),mem32        DA                 4
FISUB     r(st0),mem16        DE                 4

FISUBR    r(st0),mem32        DA                 5
FISUBR    r(st0),mem16        DE                 5

FLD       r(st0),mem32        D9                 0
FLD       r(st0),mem64        DD                 0
FLD       r(st0),mem80        DB                 5
FLD       fpureg              D9,C0              f

FLD1      r(st0)              D9,E8

FLDCW     rm                  D9                 5